| /drivers/net/ethernet/marvell/octeontx2/nic/ |
| A D | otx2_dcbnl.c | 13 u8 pfc_en = pfvf->pfc_en; in otx2_check_pfc_config() local
30 u8 pfc_en, pfc_bit_set; in otx2_pfc_txschq_config() local
33 pfc_en = pfvf->pfc_en; in otx2_pfc_txschq_config()
106 u8 pfc_en = pfvf->pfc_en; in otx2_pfc_txschq_alloc() local
202 u8 pfc_en = pfvf->pfc_en, pfc_bit_set; in otx2_pfc_txschq_update() local
272 pfc_en = pfvf->pfc_en; in otx2_pfc_txschq_stop()
313 req->pfc_en = pfvf->pfc_en; in otx2_config_priority_flow_ctrl()
405 pfc->pfc_en = pfvf->pfc_en; in otx2_dcbnl_ieee_getpfc()
417 pfvf->pfc_en = pfc->pfc_en; in otx2_dcbnl_ieee_setpfc()
442 if (pfc->pfc_en) in otx2_dcbnl_ieee_setpfc()
[all …]
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| /drivers/net/ethernet/freescale/dpaa2/ |
| A D | dpaa2-eth-dcb.c | 20 static inline bool dpaa2_eth_is_prio_enabled(u8 pfc_en, u8 tc) in dpaa2_eth_is_prio_enabled() argument
22 return !!(pfc_en & (1 << tc)); in dpaa2_eth_is_prio_enabled()
25 static int dpaa2_eth_set_pfc_cn(struct dpaa2_eth_priv *priv, u8 pfc_en) in dpaa2_eth_set_pfc_cn() argument
36 if (dpaa2_eth_is_prio_enabled(pfc_en, i)) { in dpaa2_eth_set_pfc_cn()
73 if (priv->pfc.pfc_en == pfc->pfc_en) in dpaa2_eth_dcbnl_ieee_setpfc()
85 if (pfc->pfc_en) in dpaa2_eth_dcbnl_ieee_setpfc()
96 err = dpaa2_eth_set_pfc_cn(priv, pfc->pfc_en); in dpaa2_eth_dcbnl_ieee_setpfc()
101 priv->pfc_enabled = !!pfc->pfc_en; in dpaa2_eth_dcbnl_ieee_setpfc()
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| /drivers/net/ethernet/intel/ixgbe/ |
| A D | ixgbe_dcb.c | 162 void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en) in ixgbe_dcb_unpack_pfc() argument
167 for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) { in ixgbe_dcb_unpack_pfc()
169 *pfc_en |= BIT(tc); in ixgbe_dcb_unpack_pfc()
253 u8 pfc_en; in ixgbe_dcb_hw_config() local
261 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en); in ixgbe_dcb_hw_config()
270 return ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max, in ixgbe_dcb_hw_config()
277 return ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max, in ixgbe_dcb_hw_config()
286 int ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) in ixgbe_dcb_hw_pfc_config() argument
290 return ixgbe_dcb_config_pfc_82598(hw, pfc_en); in ixgbe_dcb_hw_pfc_config()
296 return ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); in ixgbe_dcb_hw_pfc_config()
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| A D | ixgbe_dcb_82599.c | 190 int ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) in ixgbe_dcb_config_pfc_82599() argument
210 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; in ixgbe_dcb_config_pfc_82599()
212 if (pfc_en) in ixgbe_dcb_config_pfc_82599()
228 if ((prio_tc[j] == i) && (pfc_en & BIT(j))) { in ixgbe_dcb_config_pfc_82599()
333 int ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, in ixgbe_dcb_hw_config_82599() argument
342 ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); in ixgbe_dcb_hw_config_82599()
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| A D | ixgbe_dcb_82598.c | 166 int ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) in ixgbe_dcb_config_pfc_82598() argument
181 if (pfc_en) in ixgbe_dcb_config_pfc_82598()
188 if (!(pfc_en & BIT(i))) { in ixgbe_dcb_config_pfc_82598()
255 int ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, in ixgbe_dcb_hw_config_82598() argument
263 ixgbe_dcb_config_pfc_82598(hw, pfc_en); in ixgbe_dcb_hw_config_82598()
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| A D | ixgbe_dcb_82598.h | 49 int ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en);
61 int ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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| A D | ixgbe_dcb_82599.h | 73 int ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc);
87 int ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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| A D | ixgbe_dcb.h | 118 void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en);
134 int ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *tc_prio);
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| A D | ixgbe_dcb_nl.c | 347 u8 pfc_en; in ixgbe_dcbnl_set_all() local
351 ixgbe_dcb_unpack_pfc(dcb_cfg, &pfc_en); in ixgbe_dcbnl_set_all()
352 ixgbe_dcb_hw_pfc_config(hw, pfc_en, prio_tc); in ixgbe_dcbnl_set_all()
572 pfc->pfc_en = my_pfc->pfc_en; in ixgbe_dcbnl_ieee_getpfc()
606 if (pfc->pfc_en) in ixgbe_dcbnl_ieee_setpfc()
607 err = ixgbe_dcb_hw_pfc_config(hw, pfc->pfc_en, prio_tc); in ixgbe_dcbnl_ieee_setpfc()
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| /drivers/net/ethernet/intel/fm10k/ |
| A D | fm10k_dcbnl.c | 83 pfc->pfc_en = interface->pfc_en; in fm10k_dcbnl_ieee_getpfc()
98 interface->pfc_en = pfc->pfc_en; in fm10k_dcbnl_ieee_setpfc()
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| /drivers/net/ethernet/amd/xgbe/ |
| A D | xgbe-dcb.c | 110 pfc->pfc_en = pdata->pfc->pfc_en; in xgbe_dcb_ieee_getpfc()
125 pfc->pfc_cap, pfc->pfc_en, pfc->mbc, pfc->delay); in xgbe_dcb_ieee_setpfc()
128 if (pfc->pfc_en & ~((1 << pdata->hw_feat.tc_cnt) - 1)) { in xgbe_dcb_ieee_setpfc()
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| /drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| A D | hclge_dcb.c | 311 pfc->pfc_en = hdev->tm_info.pfc_en; in hclge_ieee_getpfc()
338 if (pfc->pfc_en == hdev->tm_info.pfc_en) in hclge_ieee_setpfc()
346 if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) { in hclge_ieee_setpfc()
354 hdev->tm_info.pfc_en = pfc->pfc_en; in hclge_ieee_setpfc()
358 pfc->pfc_en, pfc_map, hdev->tm_info.num_tc); in hclge_ieee_setpfc()
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| /drivers/net/ethernet/mellanox/mlx5/core/en/ |
| A D | port_buffer.c | 413 u8 pfc_en, u8 *buffer, u32 xoff, u16 port_buff_cell_sz, in update_buffer_lossy() argument
434 lossy_count += !(pfc_en & (1 << prio)); in update_buffer_lossy()
463 static int fill_pfc_en(struct mlx5_core_dev *mdev, u8 *pfc_en) in fill_pfc_en() argument
476 *pfc_en = 0xff; in fill_pfc_en()
478 err = mlx5_query_port_pfc(mdev, pfc_en, NULL); in fill_pfc_en()
519 __func__, pfc->pfc_en); in mlx5e_port_manual_buffer_config()
524 err = update_buffer_lossy(priv->mdev, max_mtu, pfc->pfc_en, buffer, xoff, in mlx5e_port_manual_buffer_config()
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| /drivers/net/ethernet/mellanox/mlx5/core/ |
| A D | en_dcbnl.c | 359 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL); in mlx5e_dcbnl_ieee_getpfc()
375 if (pfc->pfc_en != curr_pfc_en) { in mlx5e_dcbnl_ieee_setpfc()
376 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en); in mlx5e_dcbnl_ieee_setpfc()
391 pfc_new.pfc_en = (changed & MLX5E_PORT_BUFFER_PFC) ? pfc->pfc_en : curr_pfc_en; in mlx5e_dcbnl_ieee_setpfc()
404 __func__, pfc->pfc_en); in mlx5e_dcbnl_ieee_setpfc()
663 pfc.pfc_en = 0; in mlx5e_dcbnl_setall()
666 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i; in mlx5e_dcbnl_setall()
804 *setting = (pfc.pfc_en >> priority) & 0x01; in mlx5e_dcbnl_get_priority_pfc()
892 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN; in mlx5e_dcbnl_getpfcstate()
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| /drivers/net/ethernet/mellanox/mlx4/ |
| A D | en_dcb_nl.c | 403 pfc->pfc_en = priv->prof->tx_ppp; in mlx4_en_dcbnl_ieee_getpfc()
419 pfc->pfc_en, in mlx4_en_dcbnl_ieee_setpfc()
423 rx_pause = prof->rx_pause && !pfc->pfc_en; in mlx4_en_dcbnl_ieee_setpfc()
424 tx_pause = prof->tx_pause && !pfc->pfc_en; in mlx4_en_dcbnl_ieee_setpfc()
425 rx_ppp = pfc->pfc_en; in mlx4_en_dcbnl_ieee_setpfc()
426 tx_ppp = pfc->pfc_en; in mlx4_en_dcbnl_ieee_setpfc()
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| A D | rpm.c | 214 unsigned long pfc_en, in rpm_cfg_pfc_quanta_thresh() argument
221 for_each_set_bit(i, &pfc_en, 16) { in rpm_cfg_pfc_quanta_thresh()
633 int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en) in rpm_lmac_pfc_config() argument
646 pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en); in rpm_lmac_pfc_config()
657 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, pfc_en, true); in rpm_lmac_pfc_config()
659 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, class_en); in rpm_lmac_pfc_config()
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| A D | lmac_common.h | 125 u8 tx_pause, u8 rx_pause, u16 pfc_en);
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| A D | rpm.h | 136 u16 pfc_en);
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| A D | cgx.h | 187 u16 pfc_en);
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| /drivers/net/ethernet/intel/i40e/ |
| A D | i40e_dcb.c | 1368 u8 pfc_en, u8 *prio_tc) in i40e_dcb_hw_pfc_config() argument
1380 if (pfc_en & BIT(i)) { in i40e_dcb_hw_pfc_config()
1396 if (pfc_en) { in i40e_dcb_hw_pfc_config()
1399 pfc_en); in i40e_dcb_hw_pfc_config()
1405 if (pfc_en) in i40e_dcb_hw_pfc_config()
1426 pfc_en); in i40e_dcb_hw_pfc_config()
1432 pfc_en); in i40e_dcb_hw_pfc_config()
1438 if (pfc_en) { in i40e_dcb_hw_pfc_config()
1564 u8 pfc_en, u32 *mfs_tc, in i40e_dcb_hw_calculate_pool_sizes() argument
1593 if (pfc_en & BIT(i)) { in i40e_dcb_hw_calculate_pool_sizes()
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| A D | i40e_dcb.h | 254 u8 pfc_en, u8 *prio_tc);
261 u8 pfc_en, u32 *mfs_tc,
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| A D | spectrum_dcb.c | 525 mlxsw_reg_pfcc_prio_pack(pfcc_pl, pfc->pfc_en); in mlxsw_sp_port_pfc_set()
541 if (pause_en && pfc->pfc_en) { in mlxsw_sp_dcbnl_ieee_setpfc()
549 if (pfc->pfc_en) in mlxsw_sp_dcbnl_ieee_setpfc()
555 hdroom.prios.prio[prio].lossy = !(pfc->pfc_en & BIT(prio)); in mlxsw_sp_dcbnl_ieee_setpfc()
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| /drivers/net/ethernet/broadcom/bnxt/ |
| A D | bnxt_dcb.c | 263 if ((pfc->pfc_en & (1 << pri)) && in bnxt_hwrm_queue_pfc_cfg()
316 pfc->pfc_en = pri_mask; in bnxt_hwrm_queue_pfc_qcfg()
616 pfc->pfc_en = my_pfc->pfc_en; in bnxt_dcbnl_ieee_getpfc()
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| /drivers/net/ethernet/huawei/hinic/ |
| A D | hinic_port.c | 1225 int hinic_dcb_set_pfc(struct hinic_hwdev *hwdev, u8 pfc_en, u8 pfc_bitmap) in hinic_dcb_set_pfc() argument
1239 pfc.pfc_en = pfc_en; in hinic_dcb_set_pfc()
1245 pfc_en ? "enable" : "disable", err, pfc.status, in hinic_dcb_set_pfc()
1252 nic_cfg->rx_pause = pfc_en ? 0 : 1; in hinic_dcb_set_pfc()
1253 nic_cfg->tx_pause = pfc_en ? 0 : 1; in hinic_dcb_set_pfc()
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| A D | hinic_port.h | 686 u8 pfc_en; member
864 int hinic_dcb_set_pfc(struct hinic_hwdev *hwdev, u8 pfc_en, u8 pfc_bitmap);
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