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Searched refs:phy_state (Results 1 – 25 of 33) sorted by relevance

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/drivers/net/phy/
A DuPD60620.c37 int phy_state; in upd60620_read_status() local
40 phy_state = phy_read(phydev, MII_BMSR); in upd60620_read_status()
41 if (phy_state < 0) in upd60620_read_status()
42 return phy_state; in upd60620_read_status()
51 if (phy_state < 0) in upd60620_read_status()
52 return phy_state; in upd60620_read_status()
59 if (phy_state & PHY_PHYSCR_100MB) in upd60620_read_status()
61 if (phy_state & PHY_PHYSCR_DUPLEX) in upd60620_read_status()
65 if (phy_state < 0) in upd60620_read_status()
66 return phy_state; in upd60620_read_status()
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A Dphylink.c70 struct phylink_link_state phy_state; member
1429 link_state = pl->phy_state; in phylink_mac_initial_config()
1600 link_state = pl->phy_state; in phylink_resolve()
1638 if (pl->phy_state.rate_matching) { in phylink_resolve()
1640 pl->phy_state.rate_matching; in phylink_resolve()
1847 pl->phy_state.interface = iface; in phylink_create()
1939 pl->phy_state.speed = phydev->speed; in phylink_phy_change()
1942 pl->phy_state.pause = MLO_PAUSE_NONE; in phylink_phy_change()
1948 pl->phy_state.link = up; in phylink_phy_change()
2086 pl->phy_state.interface = interface; in phylink_bringup_phy()
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A Dphy.c48 static const char *phy_state_to_str(enum phy_state st) in phy_state_to_str()
65 enum phy_state old_state) in phy_process_state_change()
1517 enum phy_state old_state = phydev->state; in _phy_state_machine()
1626 enum phy_state old_state; in phy_stop()
/drivers/scsi/libsas/
A Dsas_expander.c33 ex_phy->phy_state = PHY_DEVICE_DISCOVERED; in sas_port_add_ex_phy()
225 phy->phy_state = PHY_VACANT; in sas_set_ex_phy()
228 phy->phy_state = PHY_NOT_PRESENT; in sas_set_ex_phy()
241 if (phy->phy_state == PHY_VACANT) { in sas_set_ex_phy()
633 if (phy->phy_state == PHY_VACANT || in sas_ex_disable_port()
758 if (phy->phy_state == PHY_VACANT || in sas_ex_get_linkrate()
1071 if (phy->phy_state == PHY_VACANT || in sas_find_sub_addr()
1174 if (phy->phy_state == PHY_VACANT || in sas_check_ex_subtractive_boundary()
1989 phy->phy_state = PHY_NOT_PRESENT; in sas_rediscover_dev()
1993 phy->phy_state = PHY_VACANT; in sas_rediscover_dev()
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/drivers/scsi/pm8001/
A Dpm8001_sas.c248 if (pm8001_ha->phy[phy_id].phy_state == PHY_LINK_DISABLE) { in pm8001_phy_control()
257 if (pm8001_ha->phy[phy_id].phy_state == PHY_LINK_DISABLE) { in pm8001_phy_control()
266 if (pm8001_ha->phy[phy_id].phy_state == PHY_LINK_DISABLE) { in pm8001_phy_control()
280 if (pm8001_ha->phy[phy_id].phy_state == in pm8001_phy_control()
288 if (pm8001_ha->phy[phy_id].phy_state == in pm8001_phy_control()
A Dpm8001_hwi.c109 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = in read_general_status_table()
111 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = in read_general_status_table()
113 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = in read_general_status_table()
115 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = in read_general_status_table()
117 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = in read_general_status_table()
119 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = in read_general_status_table()
121 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = in read_general_status_table()
123 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = in read_general_status_table()
3527 phy->phy_state = 1; in mpi_hw_event()
3547 phy->phy_state = 0; in mpi_hw_event()
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A Dpm8001_sas.h257 u8 phy_state; member
420 u32 phy_state[8]; member
A Dpm80xx_hwi.c3170 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in hw_event_port_recover()
3203 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in hw_event_sas_phy_up()
3285 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in hw_event_sata_phy_up()
3400 phy->phy_state = PHY_LINK_DOWN; in mpi_phy_start_resp()
3492 phy->phy_state = PHY_LINK_DISABLE; in mpi_hw_event()
3660 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in mpi_hw_event()
3695 phy->phy_state = PHY_LINK_DISABLE; in mpi_phy_stop_resp()
/drivers/net/ethernet/emulex/benet/
A Dbe_cmds.h191 #define be_phy_state_unknown(phy_state) (phy_state > BE_PHY_UNCERTIFIED) argument
192 #define be_phy_unqualified(phy_state) \ argument
193 (phy_state == BE_PHY_UNQUALIFIED || \
194 phy_state == BE_PHY_UNCERTIFIED)
195 #define be_phy_misconfigured(phy_state) \ argument
196 (phy_state == BE_PHY_INCOMPATIBLE || \
197 phy_state == BE_PHY_UNQUALIFIED || \
198 phy_state == BE_PHY_UNCERTIFIED)
A Dbe.h669 u8 phy_state; /* state of sfp optics (functional, faulted, etc.,) */ member
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c486 if (link->phy_state.symclk_ref_cnts.otg > 0) { in apply_symclk_on_tx_off_wa()
496 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in apply_symclk_on_tx_off_wa()
519 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; in dcn314_disable_link_output()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c209 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dcn401_init_hw()
729 stream->link->phy_state.symclk_ref_cnts.otg = 1; in enable_stream_timing_calc()
730 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) in enable_stream_timing_calc()
731 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in enable_stream_timing_calc()
733 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in enable_stream_timing_calc()
1041 if (dc_is_tmds_signal(signal) && link->phy_state.symclk_ref_cnts.otg > 0) { in dcn401_disable_link_output()
1043 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in dcn401_disable_link_output()
1046 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; in dcn401_disable_link_output()
1848 link->phy_state.symclk_ref_cnts.otg = 0; in dcn401_reset_back_end_for_pipe()
1849 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { in dcn401_reset_back_end_for_pipe()
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/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1553 stream->link->phy_state.symclk_ref_cnts.otg = 1; in dce110_enable_stream_timing()
1554 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) in dce110_enable_stream_timing()
1555 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in dce110_enable_stream_timing()
1557 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dce110_enable_stream_timing()
2337 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0; in dce110_reset_hw_ctx_wrap()
3244 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dce110_enable_lvds_link_output()
3260 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dce110_enable_tmds_link_output()
3322 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dce110_enable_dp_link_output()
3346 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; in dce110_disable_link_output()
/drivers/scsi/hisi_sas/
A Dhisi_sas_v2_hw.c1626 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); in get_wideport_bitmap_v2_hw() local
1629 if (phy_state & 1 << i) in get_wideport_bitmap_v2_hw()
1636 if (phy_state & 1 << 8) in get_wideport_bitmap_v2_hw()
2734 u32 phy_state, sl_ctrl, txid_auto; in phy_down_v2_hw() local
2742 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); in phy_down_v2_hw()
2743 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); in phy_down_v2_hw()
2744 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0, in phy_down_v2_hw()
A Dhisi_sas_v3_hw.c1153 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); in get_wideport_bitmap_v3_hw() local
1156 if (phy_state & BIT(i)) in get_wideport_bitmap_v3_hw()
1700 u32 phy_state, sl_ctrl, txid_auto; in phy_down_v3_hw() local
1708 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); in phy_down_v3_hw()
1709 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); in phy_down_v3_hw()
1710 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0, in phy_down_v3_hw()
1756 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); in int_phy_up_down_bcast_v3_hw() local
1757 int rdy = phy_state & (1 << phy_no); in int_phy_up_down_bcast_v3_hw()
A Dhisi_sas.h466 u32 phy_state; member
A Dhisi_sas_v1_hw.c1440 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); in int_abnormal_v1_hw() local
1443 (phy_state & 1 << phy_no) ? 1 : 0, in int_abnormal_v1_hw()
A Dhisi_sas_main.c1569 hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba); in hisi_sas_controller_reset_prepare()
1618 if (!(hisi_hba->phy_state & BIT(phy_no))) { in hisi_sas_controller_reset_done()
1638 hisi_sas_rescan_topology(hisi_hba, hisi_hba->phy_state); in hisi_sas_controller_reset_done()
/drivers/net/fddi/
A Ddefza.h553 u32 phy_state; /* PHY state */ member
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c845 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dcn32_init_hw()
1375 if (link->phy_state.symclk_ref_cnts.otg > 0) { in apply_symclk_on_tx_off_wa()
1385 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in apply_symclk_on_tx_off_wa()
1408 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; in dcn32_disable_link_output()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c904 stream->link->phy_state.symclk_ref_cnts.otg = 1; in dcn20_enable_stream_timing()
905 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) in dcn20_enable_stream_timing()
906 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in dcn20_enable_stream_timing()
908 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dcn20_enable_stream_timing()
2866 link->phy_state.symclk_ref_cnts.otg = 0; in dcn20_reset_back_end_for_pipe()
2867 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { in dcn20_reset_back_end_for_pipe()
2870 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; in dcn20_reset_back_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h1151 struct phy_state { struct
A Ddc.h1649 struct phy_state phy_state; member
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1176 stream->link->phy_state.symclk_ref_cnts.otg = 1; in dcn10_enable_stream_timing()
1177 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) in dcn10_enable_stream_timing()
1178 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; in dcn10_enable_stream_timing()
1180 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; in dcn10_enable_stream_timing()
1299 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; in dcn10_reset_back_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_hwseq.c550 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; in dcn31_reset_back_end_for_pipe()

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