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Searched refs:phy_write (Results 1 – 25 of 74) sorted by relevance

123

/drivers/net/phy/
A Dvitesse.c226 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
228 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
248 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
250 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
251 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
254 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
255 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
257 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
281 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
282 phy_write(phydev, 0x12, 0x0048); in vsc738x_config_init()
[all …]
A Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
60 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
61 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
108 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
130 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
131 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN)); in ns_giga_speed_fallback()
[all …]
A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
A Dbcm7xxx.c79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
382 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
715 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
719 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
[all …]
A Dmeson-gxl.c48 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
51 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
54 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
57 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
62 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
74 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
98 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
102 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
A Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
159 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
A Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
340 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
A Dmicrochip.c225 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
277 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
281 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
282 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
339 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
343 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
345 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */ in lan88xx_link_change_notify()
353 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
A Dbcm63xx.c34 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
37 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
60 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
69 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
A Dcicada.c67 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
73 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
95 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
98 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
A Dlxt.c88 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
90 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
129 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
152 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
154 err = phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
292 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
A Ddp83869.c222 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
224 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
350 return phy_write(phydev, MII_DP83869_MICR, val_micr); in dp83869_set_wol()
634 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); in dp83869_configure_rgmii()
723 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); in dp83869_configure_mode()
733 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
760 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
771 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
777 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
822 phy_write(phydev, DP83869_CFG4, val); in dp83869_config_init()
[all …]
A Dbcm-phy-lib.c129 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
136 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
153 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
160 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
198 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
201 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
252 return phy_write(phydev, MII_BCM54XX_SHD, in bcm_phy_write_shadow()
595 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); in bcm_phy_28nm_a0b0_afe_config_init()
659 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in _bcm_phy_cable_test_start()
660 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); in _bcm_phy_cable_test_start()
[all …]
A Dmarvell.c495 err = phy_write(phydev, 0x1d, 0x1f); in m88e1101_config_aneg()
499 err = phy_write(phydev, 0x1e, 0x200c); in m88e1101_config_aneg()
503 err = phy_write(phydev, 0x1d, 0x5); in m88e1101_config_aneg()
507 err = phy_write(phydev, 0x1e, 0); in m88e1101_config_aneg()
511 err = phy_write(phydev, 0x1e, 0x100); in m88e1101_config_aneg()
1319 err = phy_write(phydev, 07, 0xC00D); in m88e1510_config_init()
1457 err = phy_write(phydev, 0x1d, 0x3); in m88e1145_config_init_rgmii()
1621 err = phy_write(phydev, MII_BMCR, in m88e6390_errata()
2583 ret = phy_write(phydev, MII_BMCR, in m88e3082_vct_cable_test_start()
2596 ret = phy_write(phydev, 30, 0x0); in m88e3082_vct_cable_test_start()
[all …]
A Dqsemi.c71 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
110 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
113 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
A Dste10Xp.c40 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
72 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK); in ste10Xp_config_intr()
74 err = phy_write(phydev, MII_XIE, 0); in ste10Xp_config_intr()
A Dbcm-cygnus.c25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
55 rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02); in bcm_cygnus_afe_config()
85 rc = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_cygnus_config_init()
93 rc = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm_cygnus_config_init()
A Ddp83848.c77 ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK); in dp83848_config_intr()
81 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
84 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
A Det1011c.c56 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET); in et1011c_config_aneg()
76 phy_write(phydev, ET1011C_CONFIG_REG, val | in et1011c_read_status()
A Damd.c61 err = phy_write(phydev, MII_AM79C_IR, MII_AM79C_IR_IMASK_INIT); in am79c_config_intr()
63 err = phy_write(phydev, MII_AM79C_IR, 0); in am79c_config_intr()
/drivers/net/ethernet/realtek/
A Dr8169_phy_config.c297 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
435 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
436 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
438 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
452 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_common()
478 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
490 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
495 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
498 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_1_hw_phy_config()
516 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_2_hw_phy_config()
[all …]
/drivers/net/ethernet/ibm/emac/
A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
370 phy_write(phy, 0x14, 0x0ce3); in m88e1111_init()
371 phy_write(phy, 0x18, 0x4101); in m88e1111_init()
372 phy_write(phy, 0x09, 0x0e00); in m88e1111_init()
373 phy_write(phy, 0x04, 0x01e1); in m88e1111_init()
374 phy_write(phy, 0x00, 0x9140); in m88e1111_init()
[all …]
/drivers/phy/freescale/
A Dphy-fsl-imx8-mipi-dphy.c366 phy_write(phy, 0x00, DPHY_LOCK_BYP); in mixel_dphy_configure_mipi_dphy()
371 phy_write(phy, 0x25, DPHY_TST); in mixel_dphy_configure_mipi_dphy()
433 phy_write(phy, __ffs(co), DPHY_CO); in mixel_dphy_configure_lvds_phy()
505 phy_write(phy, PWR_OFF, DPHY_PD_PLL); in mixel_dphy_init()
513 phy_write(phy, 0, DPHY_CM); in mixel_dphy_exit()
514 phy_write(phy, 0, DPHY_CN); in mixel_dphy_exit()
515 phy_write(phy, 0, DPHY_CO); in mixel_dphy_exit()
526 phy_write(phy, PWR_ON, DPHY_PD_PLL); in mixel_dphy_power_on_mipi_dphy()
534 phy_write(phy, PWR_ON, DPHY_PD_DPHY); in mixel_dphy_power_on_mipi_dphy()
547 phy_write(phy, PWR_ON, DPHY_PD_DPHY); in mixel_dphy_power_on_lvds_phy()
[all …]
/drivers/net/phy/qcom/
A Dqcom-phy-lib.c21 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
43 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
51 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_write()
55 return phy_write(phydev, AT803X_DEBUG_DATA, data); in at803x_debug_reg_write()
189 err = phy_write(phydev, AT803X_INTR_ENABLE, value); in at803x_config_intr()
191 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); in at803x_config_intr()
475 return phy_write(phydev, AT803X_CDT, cdt_start); in at803x_cdt_start()
A Dat803x.c252 phy_write(phydev, MII_BMCR, context->bmcr); in at803x_context_restore()
253 phy_write(phydev, MII_ADVERTISE, context->advertise); in at803x_context_restore()
254 phy_write(phydev, MII_CTRL1000, context->control1000); in at803x_context_restore()
255 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); in at803x_context_restore()
256 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); in at803x_context_restore()
257 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); in at803x_context_restore()
678 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in at803x_cable_test_autoneg()
679 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); in at803x_cable_test_autoneg()
962 phy_write(phydev, MII_CTRL1000, 0); in at8031_cable_test_start()

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