Searched refs:phyclk (Results 1 – 12 of 12) sorted by relevance
| /drivers/phy/samsung/ |
| A D | phy-exynos5250-sata.c | 50 struct clk *phyclk; member
196 sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); in exynos_sata_phy_probe()
197 if (IS_ERR(sata_phy->phyclk)) { in exynos_sata_phy_probe()
199 ret = PTR_ERR(sata_phy->phyclk); in exynos_sata_phy_probe()
203 ret = clk_prepare_enable(sata_phy->phyclk); in exynos_sata_phy_probe()
228 clk_disable_unprepare(sata_phy->phyclk); in exynos_sata_phy_probe()
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| /drivers/net/wireless/ath/ath10k/ |
| A D | hw.c | 602 u32 phyclk; in ath10k_hw_qca988x_set_coverage_class() local
627 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; in ath10k_hw_qca988x_set_coverage_class()
653 if (slottime_reg % phyclk) { in ath10k_hw_qca988x_set_coverage_class()
661 slottime = slottime / phyclk; in ath10k_hw_qca988x_set_coverage_class()
675 slottime += value * 3 * phyclk; in ath10k_hw_qca988x_set_coverage_class()
682 ack_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
688 cts_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
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| /drivers/phy/freescale/ |
| A D | phy-fsl-samsung-hdmi.c | 612 struct clk *phyclk; in phy_clk_register() local
625 phyclk = devm_clk_register(dev, &phy->hw); in phy_clk_register()
626 if (IS_ERR(phyclk)) in phy_clk_register()
627 return dev_err_probe(dev, PTR_ERR(phyclk), in phy_clk_register()
630 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); in phy_clk_register()
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| /drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-hdmi.c | 245 struct clk *phyclk; member
638 ret = clk_prepare_enable(inno->phyclk); in inno_hdmi_phy_power_on()
644 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_on()
660 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_off()
1017 inno->phyclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
1018 if (IS_ERR(inno->phyclk)) { in inno_hdmi_phy_clk_register()
1019 ret = PTR_ERR(inno->phyclk); in inno_hdmi_phy_clk_register()
1024 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk); in inno_hdmi_phy_clk_register()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/ |
| A D | dml2_mcg_dcn4.c | 183 …min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phycl… in build_min_clock_table()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_soc_parameter_types.h | 125 struct dml2_clk_table phyclk; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/ |
| A D | dcn4_soc_bb.h | 110 .phyclk = {
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| A D | main.h | 366 bool phyclk; /* phy is out of reset and has clock */ member
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| A D | main.c | 755 wlc_hw->phyclk = clk; in brcms_b_core_phy_clk()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
| A D | dml2_internal_shared_types.h | 35 unsigned int phyclk; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| A D | dml2_dpmm_dcn4.c | 403 …phyclk_khz, &display_cfg->stream_programming[i].min_clocks.dcn4x.phyclk_khz, &state_table->phyclk); in map_min_clocks_to_dpm()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_dcn4_calcs.c | 8417 ((double)mode_lib->soc.clk_table.phyclk.clk_values_khz[0] / 1000), in dml_core_mode_support()
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