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Searched refs:pic_height (Results 1 – 25 of 25) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c295 DC_LOG_DSC("\tpic_height %d", pps->pic_height); in dsc_log_pps()
373 ASSERT(dsc_cfg->pic_height); in dsc_prepare_config()
383 !dsc_cfg->pic_width || !dsc_cfg->pic_height || in dsc_prepare_config()
402 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; in dsc_prepare_config()
412 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; in dsc_prepare_config()
414 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); in dsc_prepare_config()
415 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { in dsc_prepare_config()
416 …ix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc… in dsc_prepare_config()
537 reg_vals->pps.pic_height = 0; in dsc_init_reg_values()
595 PIC_HEIGHT, reg_vals->pps.pic_height); in dsc_write_to_registers()
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/drivers/media/platform/chips-media/wave5/
A Dwave5-hw.c685 info->pic_height = (reg_val & 0xffff); in wave5_get_dec_seq_result()
793 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
797 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
811 frame_height = init_info->pic_height; in wave5_vpu_dec_register_framebuffer()
1747 p_open_param->pic_height); in wave5_vpu_enc_init_seq()
1964 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1979 buf_height = ALIGN(p_open_param->pic_height, 8); in wave5_vpu_enc_register_framebuffer()
2566 u32 pic_height; in wave5_vpu_enc_check_open_param() local
2576 pic_height = open_param->pic_height; in wave5_vpu_enc_check_open_param()
2614 pic_height < W5_MIN_ENC_PIC_HEIGHT || pic_height > W5_MAX_ENC_PIC_HEIGHT) { in wave5_vpu_enc_check_open_param()
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A Dwave5-vpuapi.h370 u32 pic_height; member
578 u32 pic_height; /* height of a picture to be encoded in unit of sample */ member
A Dwave5-vpu-dec.c290 __func__, initial_info->pic_width, initial_info->pic_height, in handle_dynamic_resolution_change()
311 inst->conf_win.height = initial_info->pic_height - in handle_dynamic_resolution_change()
322 initial_info->pic_height, in handle_dynamic_resolution_change()
333 initial_info->pic_height, in handle_dynamic_resolution_change()
A Dwave5-vpuapi.c324 height < p_dec_info->initial_info.pic_height) in wave5_vpu_dec_register_frame_buffer_ex()
A Dwave5-vpu-enc.c1173 open_param->pic_height = inst->conf_win.height; in wave5_set_enc_openparam()
/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c40 to->pic_height = from->pic_height; in copy_pps_fields()
A Ddc_dsc.c1064 int pic_height; in setup_dsc_config() local
1072 pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; in setup_dsc_config()
1238 slice_height = min(policy.min_slice_height, pic_height); in setup_dsc_config()
1240 slice_height = min((int)(options->dsc_min_slice_height_override), pic_height); in setup_dsc_config()
1242 while (slice_height < pic_height && (pic_height % slice_height != 0 || in setup_dsc_config()
1254 dsc_cfg->num_slices_v = pic_height / slice_height; in setup_dsc_config()
A Ddsc.h39 uint32_t pic_height; member
/drivers/gpu/drm/i915/display/
A Dintel_vdsc_regs.h110 #define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height) argument
A Dintel_vdsc.c495 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) | in intel_dsc_pps_configure()
547 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / in intel_dsc_pps_configure()
910 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dicl_dsi.c1614 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1627 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
A Dintel_dp.c1896 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_dp_dsc_compute_params()
1898 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); in intel_dp_dsc_compute_params()
A Dintel_display.c5393 PIPE_CONF_CHECK_I(dsc.config.pic_height); in intel_pipe_config_compare()
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c143 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); in drm_dsc_pps_payload_pack()
1484 cfg->pic_width, cfg->pic_height, in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c77 data |= dsc->pic_height; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c158 ((dsc->pic_height & 0xffff) << 16); in dpu_hw_dsc_config_1_2()
/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c1006 dsc->pic_height = mode->vdisplay; in dsi_timing_setup()
1007 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); in dsi_timing_setup()
2545 int pic_height = mode->vdisplay; in msm_dsi_host_check_dsc() local
2556 if (pic_height % dsc->slice_height) { in msm_dsi_host_check_dsc()
2558 pic_height, dsc->slice_height); in msm_dsi_host_check_dsc()
/drivers/gpu/drm/amd/display/modules/power/
A Dpower_helpers.c947 uint16_t pic_height; in psr_su_set_dsc_slice_height() local
958 pic_height = stream->timing.v_addressable + in psr_su_set_dsc_slice_height()
964 slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; in psr_su_set_dsc_slice_height()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c266 PIC_HEIGHT, reg_vals->pps.pic_height); in dsc_write_to_registers()
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c104 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c837 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in link_set_dsc_on_stream()
968 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in link_set_dsc_pps_packet()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c350 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1057 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in dcn32_update_dsc_on_stream()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1664 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top in dcn20_validate_dsc()

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