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Searched refs:pic_width (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c164 if (dsc_cfg->pic_width > dsc20->max_image_width) in dsc2_validate_stream()
296 DC_LOG_DSC("\tpic_width %d", pps->pic_width); in dsc_log_pps()
372 ASSERT(dsc_cfg->pic_width); in dsc_prepare_config()
383 !dsc_cfg->pic_width || !dsc_cfg->pic_height || in dsc_prepare_config()
401 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; in dsc_prepare_config()
411 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
536 reg_vals->pps.pic_width = 0; in dsc_init_reg_values()
594 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
643 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
/drivers/media/platform/chips-media/wave5/
A Dwave5-hw.c684 info->pic_width = ((reg_val >> 16) & 0xffff); in wave5_get_dec_seq_result()
810 frame_width = init_info->pic_width; in wave5_vpu_dec_register_framebuffer()
1752 | p_open_param->pic_width); in wave5_vpu_enc_init_seq()
1963 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1969 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1978 buf_width = ALIGN(p_open_param->pic_width, 8); in wave5_vpu_enc_register_framebuffer()
1984 buf_width = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
2565 u32 pic_width; in wave5_vpu_enc_check_open_param() local
2575 pic_width = open_param->pic_width; in wave5_vpu_enc_check_open_param()
2613 if (pic_width < W5_MIN_ENC_PIC_WIDTH || pic_width > W5_MAX_ENC_PIC_WIDTH || in wave5_vpu_enc_check_open_param()
[all …]
A Dwave5-vpuapi.h369 u32 pic_width; member
577 u32 pic_width; /* width of a picture to be encoded in unit of sample */ member
A Dwave5-vpu-dec.c290 __func__, initial_info->pic_width, initial_info->pic_height, in handle_dynamic_resolution_change()
309 inst->conf_win.width = initial_info->pic_width - in handle_dynamic_resolution_change()
321 initial_info->pic_width, in handle_dynamic_resolution_change()
332 initial_info->pic_width, in handle_dynamic_resolution_change()
A Dwave5-vpuapi.c323 if (stride < p_dec_info->initial_info.pic_width || (stride % 8 != 0) || in wave5_vpu_dec_register_frame_buffer_ex()
A Dwave5-vpu-enc.c1172 open_param->pic_width = inst->conf_win.width; in wave5_set_enc_openparam()
/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c39 to->pic_width = from->pic_width; in copy_pps_fields()
A Ddc_dsc.c1058 int pic_width; in setup_dsc_config() local
1071 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; in setup_dsc_config()
1077 if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width) in setup_dsc_config()
1150 if (pic_width % max_slices_h == 0) in setup_dsc_config()
1172 while (pic_width % min_slices_h != 0 && min_slices_h <= max_slices_h) { in setup_dsc_config()
1229 slice_width = pic_width / num_slices_h; in setup_dsc_config()
A Ddsc.h38 uint32_t pic_width; member
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c280 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
281 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
496 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
545 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
909 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; in intel_dsc_get_pps_config()
A Dintel_vdsc_regs.h109 #define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width) argument
A Dicl_dsi.c1624 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
A Dintel_display.c5392 PIPE_CONF_CHECK_I(dsc.config.pic_width); in intel_pipe_config_compare()
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c146 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); in drm_dsc_pps_payload_pack()
1484 cfg->pic_width, cfg->pic_height, in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c117 if (dsc_cfg->pic_width > dsc401->max_image_width) in dsc401_validate_stream()
265 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c76 data = dsc->pic_width << 16; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c157 data = (dsc->pic_width & 0xffff) | in dpu_hw_dsc_config_1_2()
A Ddpu_encoder.c2018 int pic_width; in dpu_encoder_prep_dsc() local
2033 pic_width = dsc->pic_width; in dpu_encoder_prep_dsc()
2043 this_frame_slices = pic_width / dsc->slice_width; in dpu_encoder_prep_dsc()
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c103 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
122 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c1005 dsc->pic_width = mode->hdisplay; in dsi_timing_setup()
1007 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); in dsi_timing_setup()
2544 int pic_width = mode->hdisplay; in msm_dsi_host_check_dsc() local
2550 if (pic_width % dsc->slice_width) { in msm_dsi_host_check_dsc()
2552 pic_width, dsc->slice_width); in msm_dsi_host_check_dsc()
/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c835 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + in link_set_dsc_on_stream()
858 dsc_cfg.pic_width *= opp_cnt; in link_set_dsc_on_stream()
967 …dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h… in link_set_dsc_pps_packet()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c349 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
368 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1055 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + in dcn32_update_dsc_on_stream()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1662 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left in dcn20_validate_dsc()

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