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Searched refs:pin (Results 1 – 25 of 608) sorted by relevance

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/drivers/media/cec/core/
A Dcec-pin.c357 pin->rx_bit = pin->tx_bit = 0; in cec_pin_to_idle()
508 if (pin->tx_bit / 10 >= pin->tx_msg.len + pin->tx_extra_bytes) { in cec_pin_tx_states()
609 pin->rx_bit = pin->tx_bit; in cec_pin_tx_states()
1062 struct cec_pin *pin = adap->pin; in cec_pin_thread_func() local
1160 struct cec_pin *pin = adap->pin; in cec_pin_adap_enable() local
1195 struct cec_pin *pin = adap->pin; in cec_pin_adap_log_addr() local
1216 struct cec_pin *pin = adap->pin; in cec_pin_adap_transmit() local
1247 struct cec_pin *pin = adap->pin; in cec_pin_adap_status() local
1313 struct cec_pin *pin = adap->pin; in cec_pin_adap_monitor_all_enable() local
1321 struct cec_pin *pin = adap->pin; in cec_pin_adap_free() local
[all …]
A Dcec-pin-error-inj.c56 pin->rx_bit >= 18) in cec_pin_rx_error_inj()
57 cmd = pin->rx_msg.msg[1]; in cec_pin_rx_error_inj()
67 pin->tx_msg.len > 1) in cec_pin_tx_error_inj()
68 cmd = pin->tx_msg.msg[1]; in cec_pin_tx_error_inj()
76 struct cec_pin *pin = adap->pin; in cec_pin_error_inj_parse_line() local
92 memset(pin->error_inj, 0, sizeof(pin->error_inj)); in cec_pin_error_inj_parse_line()
93 pin->rx_toggle = pin->tx_toggle = false; in cec_pin_error_inj_parse_line()
108 pin->rx_toggle = false; in cec_pin_error_inj_parse_line()
115 pin->tx_toggle = false; in cec_pin_error_inj_parse_line()
136 cec_pin_start_timer(pin); in cec_pin_error_inj_parse_line()
[all …]
/drivers/pinctrl/renesas/
A Dpinctrl-rza1.c83 u8 pin: 4; member
100 u16 pin: 4; member
127 { .pin = 0, .func = 1 },
128 { .pin = 1, .func = 1 },
129 { .pin = 2, .func = 1 },
130 { .pin = 3, .func = 1 },
131 { .pin = 4, .func = 1 },
447 u8 pin; member
514 if (bidir_pin->pin == pin && bidir_pin->func == func) in rza1_pinmux_get_bidir()
532 if (swio_pin->port == port && swio_pin->pin == pin && in rza1_pinmux_get_swio()
[all …]
A DKconfig210 bool "pin control support for SH7203" if COMPILE_TEST
214 bool "pin control support for SH7264" if COMPILE_TEST
218 bool "pin control support for SH7269" if COMPILE_TEST
227 bool "pin control support for SH7720" if COMPILE_TEST
231 bool "pin control support for SH7722" if COMPILE_TEST
243 bool "pin control support for SH7734" if COMPILE_TEST
247 bool "pin control support for SH7757" if COMPILE_TEST
259 bool "pin control support for SH-X3" if COMPILE_TEST
263 bool "pin control support for RZ/A1"
274 bool "pin control support for RZ/A2"
[all …]
/drivers/pinctrl/qcom/
A Dpinctrl-ssbi-mpp.c178 if (pin->dtest) { in pm8xxx_mpp_update()
181 } else if (pin->input && pin->output) { in pm8xxx_mpp_update()
183 if (pin->high_z) in pm8xxx_mpp_update()
193 if (pin->dtest) in pm8xxx_mpp_update()
200 if (pin->paired) in pm8xxx_mpp_update()
211 if (pin->paired) in pm8xxx_mpp_update()
221 if (pin->dtest) { in pm8xxx_mpp_update()
227 if (pin->paired) in pm8xxx_mpp_update()
353 arg = pin->amux; in pm8xxx_pin_config_get()
500 if (!pin->input) in pm8xxx_mpp_get()
[all …]
A Dpinctrl-ssbi-gpio.c276 if (!pin->disable) in pm8xxx_pin_config_get()
298 if (pin->open_drain) in pm8xxx_pin_config_get()
337 pin->disable = 0; in pm8xxx_pin_config_set()
343 pin->disable = 0; in pm8xxx_pin_config_set()
354 pin->bias = pin->pull_up_strength; in pm8xxx_pin_config_set()
356 pin->disable = 0; in pm8xxx_pin_config_set()
360 pin->disable = 1; in pm8xxx_pin_config_set()
431 if (!pin->inverted) in pm8xxx_pin_config_set()
566 if (pin->disable) { in pm8xxx_gpio_dbg_show_one()
576 if (pin->inverted) in pm8xxx_gpio_dbg_show_one()
[all …]
/drivers/pinctrl/aspeed/
A Dpinmux-aspeed.h652 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin argument
653 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) argument
654 #define PIN_SYM(pin) pin_ ## pin argument
660 { #pin, PIN_EXPRS_PTR(pin) }
677 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
695 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
697 FUNC_GROUP_DECL(sig, pin)
719 PIN_DECL_(pin, \
726 PIN_DECL_(pin, \
734 PIN_DECL_(pin, \
[all …]
/drivers/dpll/
A Ddpll_netlink.c80 if (!pin) in dpll_msg_add_pin_handle()
243 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_msg_add_pin_prio()
265 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_pin_on_dpll_state()
307 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_pin_phase_adjust()
330 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_phase_offset()
353 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_ffo()
416 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_msg_add_pin_esync()
899 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_freq_set()
1016 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_ref_sync_state_set()
1051 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_ref_sync_state_set()
[all …]
A Ddpll_core.c83 if (ref->pin != pin) in dpll_xa_ref_pin_add()
98 ref->pin = pin; in dpll_xa_ref_pin_add()
135 if (ref->pin != pin) in dpll_xa_ref_pin_del()
492 pin = kzalloc(sizeof(*pin), GFP_KERNEL); in dpll_pin_alloc()
493 if (!pin) in dpll_pin_alloc()
510 ret = xa_alloc_cyclic(&dpll_pin_xa, &pin->id, pin, xa_limit_32b, in dpll_pin_alloc()
514 return pin; in dpll_pin_alloc()
521 kfree(pin); in dpll_pin_alloc()
747 ret = dpll_xa_ref_pin_add(&pin->parent_refs, parent, ops, priv, pin); in dpll_pin_on_pin_register()
771 dpll_xa_ref_pin_del(&pin->parent_refs, parent, ops, priv, pin); in dpll_pin_on_pin_register()
[all …]
/drivers/pinctrl/mediatek/
A Dpinctrl-mtk-common.c201 if (pin == pin_drv->pin) in mtk_find_pin_drv_grp_by_pin()
253 if (pin == devdata->spec_pupd[i].pin) { in mtk_pctrl_spec_pull_set_samereg()
449 if (grp->pin == pin) in mtk_pctrl_find_group_by_pin()
479 if (pin->pin.number == pin_num) { in mtk_pctrl_is_function_valid()
593 pin); in mtk_pctrl_dt_subnode_to_map()
947 group->name = pin->pin.name; in mtk_pctrl_build_state()
948 group->pin = pin->pin.number; in mtk_pctrl_build_state()
950 pctl->grp_names[i] = pin->pin.name; in mtk_pctrl_build_state()
968 *gpio_n = pin->pin.number; in mtk_xt_get_gpio_n()
995 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); in mtk_xt_set_gpio_as_eint()
[all …]
/drivers/dpll/zl3073x/
A Ddpll.c871 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); in zl3073x_dpll_input_pin_state_on_dpll_set()
1659 pin = kzalloc(sizeof(*pin), GFP_KERNEL); in zl3073x_dpll_pin_alloc()
1660 if (!pin) in zl3073x_dpll_pin_alloc()
1664 pin->dir = dir; in zl3073x_dpll_pin_alloc()
1665 pin->id = id; in zl3073x_dpll_pin_alloc()
1667 return pin; in zl3073x_dpll_pin_alloc()
1681 kfree(pin); in zl3073x_dpll_pin_free()
1702 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); in zl3073x_dpll_pin_register()
1711 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); in zl3073x_dpll_pin_register()
2059 pin->label, pin->phase_offset, phase_offset); in zl3073x_dpll_pin_phase_offset_check()
[all …]
/drivers/gpio/
A Dgpio-lpc32xx.c201 unsigned pin, int high) in __set_gpio_level_p012() argument
212 unsigned pin, int high) in __set_gpio_level_p3() argument
232 unsigned pin) in __get_gpio_state_p012() argument
235 pin); in __get_gpio_state_p012()
239 unsigned pin) in __get_gpio_state_p3() argument
251 unsigned pin) in __get_gpi_state_p3() argument
257 unsigned pin) in __get_gpo_state_p3() argument
266 unsigned pin) in lpc32xx_gpio_dir_input_p012() argument
276 unsigned pin) in lpc32xx_gpio_dir_input_p3() argument
286 unsigned pin) in lpc32xx_gpio_dir_in_always() argument
[all …]
A Dgpio-dln2.c65 __le16 pin; member
91 .pin = cpu_to_le16(pin), in dln2_gpio_pin_cmd()
101 .pin = cpu_to_le16(pin), in dln2_gpio_pin_val()
109 if (len < sizeof(rsp) || req.pin != rsp.pin) in dln2_gpio_pin_val()
139 .pin = cpu_to_le16(pin), in dln2_gpio_pin_set_out_val()
169 if (len < sizeof(rsp) || req.pin != rsp.pin) { in dln2_gpio_request()
290 __le16 pin; in dln2_gpio_set_event_cfg() member
294 .pin = cpu_to_le16(pin), in dln2_gpio_set_event_cfg()
403 int pin, ret; in dln2_gpio_event() local
408 __le16 pin; in dln2_gpio_event() member
[all …]
A Dgpio-zevio.c78 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) in zevio_gpio_get() argument
85 if (dir & BIT(ZEVIO_GPIO_BIT(pin))) in zevio_gpio_get()
91 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; in zevio_gpio_get()
102 val |= BIT(ZEVIO_GPIO_BIT(pin)); in zevio_gpio_set()
104 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); in zevio_gpio_set()
106 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); in zevio_gpio_set()
120 val |= BIT(ZEVIO_GPIO_BIT(pin)); in zevio_gpio_direction_input()
129 unsigned pin, int value) in zevio_gpio_direction_output() argument
137 val |= BIT(ZEVIO_GPIO_BIT(pin)); in zevio_gpio_direction_output()
139 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); in zevio_gpio_direction_output()
[all …]
/drivers/acpi/
A Dpci_irq.c28 u8 pin; member
84 unsigned char pin; member
122 entry->pin == quirk->pin && in do_prt_fixups()
146 prt->pin + 1 != pin) in acpi_pci_irq_check_entry()
161 entry->pin = prt->pin + 1; in acpi_pci_irq_check_entry()
313 pin = pci_swizzle_interrupt_pin(dev, pin); in acpi_pci_irq_lookup()
387 u8 pin; in acpi_pci_irq_enable() local
404 pin = dev->pin; in acpi_pci_irq_enable()
405 if (!pin) { in acpi_pci_irq_enable()
481 u8 pin; in acpi_pci_irq_disable() local
[all …]
/drivers/usb/misc/
A Dbrcmstb-usb-pinmap.c66 pinmap_set(pin->pdata->regs, pin->value_mask); in sync_in_pin()
68 pinmap_unset(pin->pdata->regs, pin->value_mask); in sync_in_pin()
107 sync_in_pin(pin); in brcmstb_usb_pinmap_gpio_isr()
134 struct in_pin *pin; in parse_pins() local
151 pin->name); in parse_pins()
158 pin->name); in parse_pins()
165 pin->name); in parse_pins()
169 pin++; in parse_pins()
245 pin++; in sync_all_pins()
312 pin->name); in brcmstb_usb_pinmap_probe()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_hotplug.c179 pin, in intel_hpd_irq_storm_detect()
237 enum hpd_pin pin; in intel_hpd_irq_storm_switch_to_polling() local
275 enum hpd_pin pin; in intel_hpd_irq_storm_reenable_work() local
378 enum hpd_pin pin; in get_blocked_hpd_pin_mask() local
506 enum hpd_pin pin; in i915_hotplug_work_func() local
513 hpd_bit = BIT(pin); in i915_hotplug_work_func()
594 enum hpd_pin pin; in intel_hpd_irq_handler() local
652 pin); in intel_hpd_irq_handler()
811 enum hpd_pin pin; in i915_hpd_poll_init_work() local
998 enum hpd_pin pin; in queue_work_for_missed_irqs() local
[all …]
/drivers/pinctrl/sophgo/
A Dpinctrl-cv18xx.c95 u32 pin_hwid = pin->pin.id; in cv1800_pctrl_dbg_show()
114 if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) { in cv1800_pctrl_dbg_show()
129 struct cv1800_pin *pin = sophgo_to_cv1800_pin(config->pin); in cv1800_verify_pinmux_config() local
133 if (mux > pin->mux.max) in cv1800_verify_pinmux_config()
136 if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) { in cv1800_verify_pinmux_config()
153 struct cv1800_pin *pin; in cv1800_verify_pin_group() local
161 pin = sophgo_to_cv1800_pin(mux[0].pin); in cv1800_verify_pin_group()
166 pin = sophgo_to_cv1800_pin(mux[i].pin); in cv1800_verify_pin_group()
181 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(pinmuxs[0].pin); in cv1800_dt_node_to_map_post() local
255 if (!pin) in cv1800_pconf_get()
[all …]
/drivers/pinctrl/
A Dpinctrl-zynqmp.c242 pin); in zynqmp_pinmux_release_pin()
333 pin); in zynqmp_pinconf_cfg_get()
416 pin); in zynqmp_pinconf_cfg_set()
430 pin); in zynqmp_pinconf_cfg_set()
607 for (pin = 0; pin < groups[resp[i]].npins; pin++) { in zynqmp_pinctrl_prepare_func_groups()
629 pin = 0; in zynqmp_pinctrl_prepare_func_groups()
757 for (pin = 0; pin < zynqmp_desc.npins; pin++) { in zynqmp_pinctrl_prepare_group_pins()
875 pin = &pins[i]; in zynqmp_pinctrl_prepare_pin_desc()
879 if (!pin->name) in zynqmp_pinctrl_prepare_pin_desc()
931 pin = &pins[i]; in versal_pinctrl_prepare_pin_desc()
[all …]
A Dpinctrl-at91.c384 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); in two_bit_pin_value_shift_amount()
588 sama5d3_get_drive_register(pin), pin); in at91_mux_sama5d3_get_drivestrength()
602 at91sam9x5_get_drive_register(pin), pin); in at91_mux_sam9x5_get_drivestrength()
780 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); in at91_pin_dbg()
783 pin->bank + 'A', pin->pin, pin->conf); in at91_pin_dbg()
805 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { in pin_check_config()
822 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { in pin_check_config()
824 name, index, mux, pin->bank + 'A', pin->pin); in pin_check_config()
873 mask = pin_to_mask(pin->pin); in at91_pmx_set()
1232 pin->pin = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
[all …]
A Dpinctrl-rp1.c774 if (!pin) in rp1_gpio_get()
786 if (pin) in rp1_gpio_set()
797 if (!pin) in rp1_gpio_get_direction()
813 if (!pin) in rp1_gpio_direction_input()
826 if (!pin) in rp1_gpio_direction_output()
1123 np, pin); in rp1_pctl_legacy_map_func()
1130 + pin); in rp1_pctl_legacy_map_func()
1415 if (!pin) in rp1_pinconf_set()
1494 if (!pin) in rp1_pinconf_get()
1712 pin->bank = i; in rp1_pinctrl_probe()
[all …]
A Dpinctrl-keembay.c58 #define KEEMBAY_GPIO_REG_OFFSET(pin) ((pin) * 4) argument
916 if (pin >= kpc->npins) in keembay_request_gpio()
937 int pin; in keembay_set_mux() local
948 pin = *grp->grp.pins; in keembay_set_mux()
1051 if (pin >= kpc->npins) in keembay_pinconf_get()
1105 if (pin >= kpc->npins) in keembay_pinconf_set()
1228 unsigned int pin, int value) in keembay_gpio_set_direction_out() argument
1247 unsigned int src, pin, val; in keembay_gpio_irq_handler() local
1341 int slot, irq_hw_number_t pin) in keembay_gpio_set_irq() argument
1359 irq->pins[slot] = pin; in keembay_gpio_set_irq()
[all …]
A Dpinctrl-max77620.c344 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) in max77620_set_fps_param()
378 param, pin); in max77620_set_fps_param()
441 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) in max77620_pinconf_set()
472 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) in max77620_pinconf_set()
500 BIT(pin) : 0; in max77620_pinconf_set()
612 int pin, p; in max77620_pinctrl_suspend() local
614 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { in max77620_pinctrl_suspend()
615 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) in max77620_pinctrl_suspend()
628 int pin, p; in max77620_pinctrl_resume() local
630 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { in max77620_pinctrl_resume()
[all …]
/drivers/pinctrl/sunxi/
A Dpinctrl-sunxi-dt.c169 int bank = (pin->pin.number - pin_base) / PINS_PER_BANK; in prepare_function_table()
172 pin->variant++; in prepare_function_table()
214 int bank = (pin->pin.number - pin_base) / PINS_PER_BANK; in prepare_function_table()
228 func[lastfunc].irqnum = pin->pin.number % PINS_PER_BANK; in prepare_function_table()
244 pin->variant = 2; in prepare_function_table()
262 int pin, i, index; in fill_pin_function() local
273 for (pin = 0; pin < npins; pin++) in fill_pin_function()
274 if (!strcmp(pins[pin].pin.name, name)) in fill_pin_function()
276 if (pin == npins) { in fill_pin_function()
324 func = &pins[pin].functions[pins[pin].variant]; in fill_pin_function()
[all …]
/drivers/pinctrl/meson/
A Dpinctrl-meson.c98 unsigned int pin, in meson_calc_reg_and_bit() argument
181 unsigned int pin, in meson_pinconf_set_gpio_bit() argument
199 unsigned int pin, in meson_pinconf_get_gpio_bit() argument
219 unsigned int pin, in meson_pinconf_set_output() argument
226 unsigned int pin) in meson_pinconf_get_output() argument
237 unsigned int pin, in meson_pinconf_set_drive() argument
244 unsigned int pin) in meson_pinconf_get_drive() argument
250 unsigned int pin, in meson_pinconf_set_output_drive() argument
263 unsigned int pin) in meson_pinconf_disable_bias() argument
309 unsigned int pin, in meson_pinconf_set_drive_strength() argument
[all …]

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