| /drivers/gpu/drm/i915/display/ |
| A D | intel_dp.c | 965 u32 pipe_bpp, in intel_dp_dsc_get_max_compressed_bpp() argument
1470 int pipe_bpp; in intel_dp_mode_valid() local
1499 pipe_bpp, 64); in intel_dp_mode_valid()
2161 int pipe_bpp, in dsc_compute_compressed_bpp() argument
2221 int pipe_bpp) in is_dsc_pipe_bpp_sufficient() argument
2261 int forced_bpp, pipe_bpp; in intel_dp_dsc_compute_pipe_bpp() local
2282 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) in intel_dp_dsc_compute_pipe_bpp()
2288 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_pipe_bpp()
2311 pipe_bpp = forced_bpp; in intel_edp_dsc_compute_pipe_bpp()
2336 pipe_config->pipe_bpp = pipe_bpp; in intel_edp_dsc_compute_pipe_bpp()
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| A D | intel_fdi.c | 310 int pipe_bpp = min(crtc_state->pipe_bpp, in intel_fdi_compute_pipe_bpp() local
313 pipe_bpp = rounddown(pipe_bpp, 2 * 3); in intel_fdi_compute_pipe_bpp()
315 if (pipe_bpp < 6 * 3) in intel_fdi_compute_pipe_bpp()
318 crtc_state->pipe_bpp = pipe_bpp; in intel_fdi_compute_pipe_bpp()
342 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
346 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), in ilk_fdi_compute_config()
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| A D | intel_dp.h | 39 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
95 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
144 u32 pipe_bpp,
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| A D | g4x_hdmi.c | 47 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
306 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
348 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
359 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
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| A D | intel_lvds.c | 301 if (crtc_state->dither && crtc_state->pipe_bpp == 18) in intel_pre_enable_lvds()
446 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { in intel_lvds_compute_config()
449 crtc_state->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
450 crtc_state->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
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| A D | intel_display.c | 3042 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3045 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3048 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3134 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
3379 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3382 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3385 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3388 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
4323 crtc_state->pipe_bpp); in compute_sink_pipe_bpp()
4325 crtc_state->pipe_bpp = bpp; in compute_sink_pipe_bpp()
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| A D | intel_hdmi.c | 944 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
949 switch (pipe_bpp) { in gcp_default_phase_possible()
1039 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1043 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2123 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2172 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2176 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
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| A D | intel_dp_mst.c | 431 crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16); in intel_dp_mtp_tu_compute_config()
493 crtc_state->pipe_bpp = max_bpp; in mst_stream_dsc_compute_link_config()
504 …max_compressed_bpp_x16 = min(max_compressed_bpp_x16, fxp_q4_from_int(crtc_state->pipe_bpp) - bpp_s… in mst_stream_dsc_compute_link_config()
1522 int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); in mst_connector_mode_valid_ctx() local
1533 pipe_bpp, 64); in mst_connector_mode_valid_ctx()
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| A D | hsw_ips.c | 204 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
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| A D | intel_link_bw.c | 131 link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp); in __intel_link_bw_reduce_bpp()
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| A D | icl_dsi.c | 1557 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1602 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1669 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1671 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
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| A D | intel_crt.c | 457 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { in hsw_crt_compute_config()
463 crtc_state->pipe_bpp = 24; in hsw_crt_compute_config()
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| A D | intel_ddi.c | 430 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
444 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
525 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
527 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
4117 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
4120 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
4123 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
4126 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
4181 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
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| A D | intel_crtc_state_dump.c | 209 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
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| A D | vlv_dsi.c | 299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1043 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
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| A D | intel_audio.c | 235 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
238 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
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| A D | intel_display_debugfs.c | 561 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
1226 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); in i915_current_bpc_show()
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| A D | intel_pfit.c | 536 if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
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| A D | intel_modeset_setup.c | 314 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; in intel_modeset_update_connector_atomic_state()
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| A D | intel_psr.c | 1471 max_bpp = crtc_state->pipe_bpp; in intel_psr2_config_valid()
1486 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1489 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
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| A D | intel_vdsc.c | 316 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
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| A D | g4x_dp.c | 406 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
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| A D | intel_display_types.h | 1109 int pipe_bpp; /* in 1 bpp units */ member
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| A D | intel_bios.c | 3479 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3481 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp, in fill_dsc()
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| A D | intel_tv.c | 1217 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
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