| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 994 int pipe_cnt, i; in dcn20_populate_dml_writeback_from_context() local
1026 pipe_cnt++; in dcn20_populate_dml_writeback_from_context()
1144 int pipe_cnt, in dcn20_calculate_dlg_params() argument
1239 pipe_cnt, in dcn20_calculate_dlg_params()
1320 int pipe_cnt, i; in dcn20_populate_dml_pipes_from_context() local
1331 pipe_cnt = i; in dcn20_populate_dml_pipes_from_context()
1722 pipe_cnt++; in dcn20_populate_dml_pipes_from_context()
1728 return pipe_cnt; in dcn20_populate_dml_pipes_from_context()
1777 pipe_cnt++; in dcn20_calculate_wm()
2277 pipe_cnt++; in dcn21_calculate_wm()
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| A D | dcn20_fpu.h | 38 int pipe_cnt, int i);
42 int pipe_cnt,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | dcn314_fpu.c | 311 int i, pipe_cnt; in dcn314_populate_dml_pipes_from_context_fpu() local
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn314_populate_dml_pipes_from_context_fpu()
346 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn314_populate_dml_pipes_from_context_fpu()
348 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn314_populate_dml_pipes_from_context_fpu()
370 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn314_populate_dml_pipes_from_context_fpu()
371 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn314_populate_dml_pipes_from_context_fpu()
373 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn314_populate_dml_pipes_from_context_fpu()
390 pipe_cnt++; in dcn314_populate_dml_pipes_from_context_fpu()
395 if (pipe_cnt == 1 && pipe->plane_state in dcn314_populate_dml_pipes_from_context_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 184 int pipe_cnt, i, j; in dcn30_fpu_populate_dml_writeback_from_context() local
199 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_fpu_populate_dml_writeback_from_context()
200 pipes[pipe_cnt].dout.num_active_wb = 0; in dcn30_fpu_populate_dml_writeback_from_context()
206 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_fpu_populate_dml_writeback_from_context()
257 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_fpu_populate_dml_writeback_from_context()
262 pipes[pipe_cnt].dout.wb = dout_wb; in dcn30_fpu_populate_dml_writeback_from_context()
267 pipe_cnt++; in dcn30_fpu_populate_dml_writeback_from_context()
274 int pipe_cnt, in dcn30_fpu_set_mcif_arb_params() argument
306 int pipe_cnt, in dcn30_fpu_calculate_wm_and_dlg() argument
334 context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
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| A D | dcn30_fpu.h | 38 int pipe_cnt,
46 int pipe_cnt,
66 int pipe_cnt,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 475 int i, pipe_cnt; in dcn351_populate_dml_pipes_from_context_fpu() local
501 pipes[pipe_cnt].pipe.dest.vtotal = in dcn351_populate_dml_pipes_from_context_fpu()
504 pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
507 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
508 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn351_populate_dml_pipes_from_context_fpu()
513 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn351_populate_dml_pipes_from_context_fpu()
515 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn351_populate_dml_pipes_from_context_fpu()
539 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn351_populate_dml_pipes_from_context_fpu()
543 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn351_populate_dml_pipes_from_context_fpu()
560 pipe_cnt++; in dcn351_populate_dml_pipes_from_context_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 442 int i, pipe_cnt; in dcn35_populate_dml_pipes_from_context_fpu() local
468 pipes[pipe_cnt].pipe.dest.vtotal = in dcn35_populate_dml_pipes_from_context_fpu()
471 pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
474 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
475 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn35_populate_dml_pipes_from_context_fpu()
480 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn35_populate_dml_pipes_from_context_fpu()
482 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn35_populate_dml_pipes_from_context_fpu()
506 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn35_populate_dml_pipes_from_context_fpu()
510 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn35_populate_dml_pipes_from_context_fpu()
527 pipe_cnt++; in dcn35_populate_dml_pipes_from_context_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 297 int pipe_cnt) in calculate_wm_set_for_vlevel() argument
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
318 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
415 int pipe_cnt, in dcn301_fpu_calculate_wm_and_dlg() argument
435 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
440 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
445 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
451 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
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| A D | dcn301_fpu.h | 39 int pipe_cnt,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.h | 37 int pipe_cnt);
44 unsigned int pipe_cnt,
56 int pipe_cnt,
64 int pipe_cnt,
70 int pipe_cnt);
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| A D | dcn32_fpu.c | 278 int pipe_cnt, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
336 int pipe_cnt) in dcn32_helper_populate_phantom_dlg_params() argument
471 unsigned int pipe_cnt, in dcn32_set_phantom_stream_timing() argument
1400 int pipe_cnt) in try_odm_power_optimization_and_revalidate() argument
1443 int *pipe_cnt, in dcn32_full_validate_bw_helper() argument
1801 pipe_cnt, pipe_idx); in dcn32_calculate_dlg_params()
2149 int pipe_cnt, i, pipe_idx; in dcn32_internal_validate_bw() local
2169 if (!pipe_cnt) { in dcn32_internal_validate_bw()
2289 *pipe_cnt_out = pipe_cnt; in dcn32_internal_validate_bw()
2304 int pipe_cnt, in dcn32_calculate_wm_and_dlg_fpu() argument
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 446 int pipe_cnt) in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
485 int pipe_cnt, in dcn31_calculate_wm_and_dlg_fp() argument
501 if (pipe_cnt == 0) { in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
513 …if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_tim… in dcn31_calculate_wm_and_dlg_fp()
523 …bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
544 …pes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn31_calculate_wm_and_dlg_fp()
559 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
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| A D | dcn31_fpu.h | 36 int pipe_cnt);
44 int pipe_cnt,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 318 uint8_t pipe_cnt = 0; in dcn32_determine_det_override() local
369 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
373 pipe_cnt++; in dcn32_determine_det_override()
384 int i, pipe_cnt; in dcn32_set_det_allocations() local
389 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_det_allocations()
395 pipe_cnt++; in dcn32_set_det_allocations()
402 if (pipe_cnt == 1) { in dcn32_set_det_allocations()
753 int i, pipe_cnt; in dcn32_update_dml_pipes_odm_policy_based_on_context() local
757 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_dml_pipes_odm_policy_based_on_context()
766 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; in dcn32_update_dml_pipes_odm_policy_based_on_context()
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| A D | dcn32_resource.c | 1686 unsigned int pipe_cnt, in dcn32_enable_phantom_stream() argument
1713 unsigned int pipe_cnt, in dcn32_add_phantom_pipes() argument
1752 int pipe_cnt = 0; in dml1_validate() local
1773 if (pipe_cnt == 0) in dml1_validate()
1867 int i, pipe_cnt; in dcn32_populate_dml_pipes_from_context() local
1910 pipe_cnt++; in dcn32_populate_dml_pipes_from_context()
1921 pipes[pipe_cnt].pipe.src.gpuvm = true; in dcn32_populate_dml_pipes_from_context()
1985 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn32_populate_dml_pipes_from_context()
2003 pipe_cnt++; in dcn32_populate_dml_pipes_from_context()
2020 return pipe_cnt; in dcn32_populate_dml_pipes_from_context()
[all …]
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 1669 int i, pipe_cnt, crb_idx, crb_pipes; in dcn315_populate_dml_pipes_from_context() local
1697 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn315_populate_dml_pipes_from_context()
1698 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn315_populate_dml_pipes_from_context()
1725 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn315_populate_dml_pipes_from_context()
1728 pipes[pipe_cnt].dout.dsc_input_bpc = 8; in dcn315_populate_dml_pipes_from_context()
1741 pipe_cnt++; in dcn315_populate_dml_pipes_from_context()
1754 pipe_cnt++; in dcn315_populate_dml_pipes_from_context()
1772 pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; in dcn315_populate_dml_pipes_from_context()
1778 pipe_cnt++; in dcn315_populate_dml_pipes_from_context()
1782 if (pipe_cnt) in dcn315_populate_dml_pipes_from_context()
[all …]
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1621 uint32_t pipe_cnt; in dcn31x_populate_dml_pipes_from_context() local
1628 for (i = 0; i < pipe_cnt; i++) { in dcn31x_populate_dml_pipes_from_context()
1638 return pipe_cnt; in dcn31x_populate_dml_pipes_from_context()
1646 int i, pipe_cnt; in dcn31_populate_dml_pipes_from_context() local
1674 pipes[pipe_cnt].pipe.src.gpuvm = true; in dcn31_populate_dml_pipes_from_context()
1700 pipe_cnt++; in dcn31_populate_dml_pipes_from_context()
1720 return pipe_cnt; in dcn31_populate_dml_pipes_from_context()
1732 int pipe_cnt, in dcn31_calculate_wm_and_dlg() argument
1754 int pipe_cnt) in dcn31_set_mcif_arb_params() argument
1770 int pipe_cnt = 0; in dcn31_validate_bandwidth() local
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| A D | dcn31_resource.h | 46 int pipe_cnt,
60 int pipe_cnt);
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.h | 52 int pipe_cnt);
72 int pipe_cnt,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| A D | dcn30_resource.c | 1324 int i, pipe_cnt; in dcn30_populate_dml_pipes_from_context() local
1335 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = in dcn30_populate_dml_pipes_from_context()
1339 return pipe_cnt; in dcn30_populate_dml_pipes_from_context()
1377 int pipe_cnt) in dcn30_set_mcif_arb_params() argument
1638 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1651 if (!pipe_cnt) { in dcn30_internal_validate_bw()
1656 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1871 *pipe_cnt_out = pipe_cnt; in dcn30_internal_validate_bw()
2030 int pipe_cnt, in dcn30_calculate_wm_and_dlg() argument
2047 int pipe_cnt = 0; in dcn30_validate_bandwidth() local
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 1615 int i, pipe_cnt; in dcn316_populate_dml_pipes_from_context() local
1641 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn316_populate_dml_pipes_from_context()
1642 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn316_populate_dml_pipes_from_context()
1644 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); in dcn316_populate_dml_pipes_from_context()
1647 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn316_populate_dml_pipes_from_context()
1650 pipes[pipe_cnt].dout.dsc_input_bpc = 8; in dcn316_populate_dml_pipes_from_context()
1653 pipes[pipe_cnt].dout.dsc_input_bpc = 10; in dcn316_populate_dml_pipes_from_context()
1656 pipes[pipe_cnt].dout.dsc_input_bpc = 12; in dcn316_populate_dml_pipes_from_context()
1664 pipe_cnt++; in dcn316_populate_dml_pipes_from_context()
1667 if (pipe_cnt) in dcn316_populate_dml_pipes_from_context()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 91 int pipe_cnt,
186 int pipe_cnt);
212 unsigned int pipe_cnt,
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| /drivers/usb/host/ |
| A D | r8a66597.h | 79 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; member
120 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; member
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_lib.h | 106 int pipe_cnt);
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.h | 122 …xt, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);
|