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Searched refs:pipe_control_lock (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hwss/dce80/
A Ddce80_hwseq.c50 dc->hwss.pipe_control_lock = dce_pipe_control_lock; in dce80_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_init.c57 .pipe_control_lock = dcn10_pipe_control_lock,
A Ddcn10_hwseq.c245 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
247 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_init.c58 .pipe_control_lock = dcn201_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_init.c59 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn301/
A Ddcn301_init.c61 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
A Ddcn21_init.c59 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_init.c60 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_init.c65 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_init.c63 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
A Ddcn351_init.c66 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_init.c41 .pipe_control_lock = dcn20_pipe_control_lock,
A Ddcn401_hwseq.c1688 dc->hwss.pipe_control_lock(dc, pipe, true); in dcn401_interdependent_update_lock()
1704 dc->hwss.pipe_control_lock(dc, pipe, false); in dcn401_interdependent_update_lock()
1723 dc->hwss.pipe_control_lock(dc, pipe, false); in dcn401_interdependent_update_lock()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_init.c62 .pipe_control_lock = dcn20_pipe_control_lock,
A Ddcn32_hwseq.c1833 dc->hwss.pipe_control_lock(dc, pipe, true); in dcn32_interdependent_update_lock()
1835 dc->hwss.pipe_control_lock(dc, pipe, false); in dcn32_interdependent_update_lock()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_init.c67 .pipe_control_lock = dcn20_pipe_control_lock,
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_hw_sequencer.c765 if (dc->hwss.pipe_control_lock) { in hwss_build_fast_sequence()
882 if (dc->hwss.pipe_control_lock) { in hwss_build_fast_sequence()
940 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc, in hwss_execute_sequence()
A Ddc.c1199 dc->hwss.pipe_control_lock(dc, pipe_ctx, lock); in apply_ctx_interdependent_lock()
4160 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); in commit_planes_for_stream()
4182 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); in commit_planes_for_stream()
4372 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); in commit_planes_for_stream()
/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c428 dc->hwss.pipe_control_lock = dce60_pipe_control_lock; in dce60_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h251 void (*pipe_control_lock)(struct dc *dc, member
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c3378 .pipe_control_lock = dce_pipe_control_lock,

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