| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
349 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
376 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn32_determine_det_override()
655 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_drr_admissable()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
148 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
289 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
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| A D | dc.c | 1302 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1406 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1478 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1571 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1574 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1597 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1600 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1609 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1623 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
2023 for (i = 0; i < dc->res_pool->pipe_count; i++) { in get_stream_mask()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1106 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1855 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
2240 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create() local
2242 for (i = 0; i < pipe_count; i++) { in dcn20_dwbc_create()
2263 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create() local
2265 ASSERT(pipe_count > 0); in dcn20_mmhubbub_create()
2267 for (i = 0; i < pipe_count; i++) { in dcn20_mmhubbub_create()
2412 pool->base.pipe_count = 5; in dcn20_resource_construct()
2416 pool->base.pipe_count = 6; in dcn20_resource_construct()
2616 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_hw()
717 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
744 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
772 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
836 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
1027 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_gate()
1116 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_ungate()
1205 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_ungate()
1278 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_hw_block_power_down()
1361 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_hw_block_power_up()
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| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 801 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
874 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1038 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1100 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1158 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1236 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1298 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1356 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1433 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 807 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
880 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
966 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1048 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1110 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1168 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1248 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1310 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1368 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1445 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 231 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
353 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
384 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
405 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
606 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
625 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
671 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_mall_sel()
731 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_program_mall_pipe_config()
946 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_init_hw()
1248 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_resync_fifo_dccg_dio()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 1097 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1178 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1218 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1220 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1243 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1245 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1386 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1510 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1721 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2468 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| A D | dce110_resource.c | 816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
979 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1270 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1271 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1272 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1273 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1274 pool->pipe_count++; in underlay_create()
1368 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1369 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1444 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 710 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
712 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
745 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
747 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
965 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
966 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1021 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1096 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1217 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1371 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 672 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
674 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
707 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
709 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
911 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
912 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
966 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1041 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1159 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1304 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 134 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
204 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
249 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
303 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
342 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
513 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 564 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
575 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
686 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
736 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
818 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
835 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
924 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_vblank_schedulable()
994 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_admissable()
1098 for (i = 0; i < dc->res_pool->pipe_count; i++) { in assign_subvp_index()
1604 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 1068 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1178 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1180 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1203 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1205 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1303 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1432 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1587 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
1630 pool->base.pipe_count = j; in dcn301_resource_construct()
1704 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| A D | dcn35_pg_cntl.c | 411 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
443 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
486 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
496 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 228 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
333 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
363 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
389 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
421 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
451 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_color_state()
1302 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn10_reset_back_end_for_pipe()
1306 if (i == dc->res_pool->pipe_count) in dcn10_reset_back_end_for_pipe()
3512 for (i = 0; i < res_pool->pipe_count; i++) { in get_hubp_by_inst()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 88 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
2066 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2081 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2088 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2106 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2114 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2142 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2155 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2248 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
2254 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 310 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_init_hw()
1237 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_calculate_cab_allocation()
2105 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2120 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_program_front_end_for_ctx()
2127 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2145 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_program_front_end_for_ctx()
2154 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_program_front_end_for_ctx()
2182 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2195 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2253 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_post_unlock_program_front_end()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| A D | dce60_hwseq.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1398 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1518 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1543 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1655 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1901 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2067 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_construct()
2202 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
2241 uint8_t pipe_count, in dcn31_update_dc_state_for_encoder_switch() argument
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 919 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1344 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1347 pool->base.pipe_count = 3; in dcn10_resource_construct()
1560 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1629 pool->base.pipe_count = j; in dcn10_resource_construct()
1636 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1637 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1658 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 275 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn351_update_bw_bounding_box_fpu()
484 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
589 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
616 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_decide_zstate_support()
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