Searched refs:pipe_dlg_param (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 258 pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst; in populate_pipe_ctx_dlg_params_from_dml()
260 pipe_ctx->pipe_dlg_param.hactive = hactive; in populate_pipe_ctx_dlg_params_from_dml()
261 pipe_ctx->pipe_dlg_param.vactive = vactive; in populate_pipe_ctx_dlg_params_from_dml()
262 pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total; in populate_pipe_ctx_dlg_params_from_dml()
263 pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total; in populate_pipe_ctx_dlg_params_from_dml()
264 pipe_ctx->pipe_dlg_param.hblank_end = hblank_end; in populate_pipe_ctx_dlg_params_from_dml()
265 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; in populate_pipe_ctx_dlg_params_from_dml()
266 pipe_ctx->pipe_dlg_param.hblank_start = hblank_start; in populate_pipe_ctx_dlg_params_from_dml()
267 pipe_ctx->pipe_dlg_param.vblank_start = vblank_start; in populate_pipe_ctx_dlg_params_from_dml()
271 pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max; in populate_pipe_ctx_dlg_params_from_dml()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1212 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1214 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
1215 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
1231 pipe->pipe_dlg_param.vblank_start = asic_blank_start; in dcn_validate_bandwidth()
1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1257 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; in dcn_validate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 917 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
918 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
919 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn20_enable_stream_timing()
920 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_enable_stream_timing()
1565 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1566 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start in dcn20_detect_pipe_changes()
1567 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset in dcn20_detect_pipe_changes()
1568 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) in dcn20_detect_pipe_changes()
1710 &pipe_ctx->pipe_dlg_param); in dcn20_update_dchubp_dpp()
1906 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_program_tg()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 138 vblank_start = pipe_ctx->pipe_dlg_param.vblank_start; in dcn10_wait_for_pipe_update_if_needed()
1187 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_enable_stream_timing()
1188 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_enable_stream_timing()
1189 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn10_enable_stream_timing()
1190 pipe_ctx->pipe_dlg_param.pstate_keepout, in dcn10_enable_stream_timing()
3022 &pipe_ctx->pipe_dlg_param); in dcn10_update_dchubp_dpp()
3179 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_program_pipe()
3180 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_program_pipe()
3181 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn10_program_pipe()
3182 pipe_ctx->pipe_dlg_param.pstate_keepout); in dcn10_program_pipe()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 476 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 1268 return pipe_ctx->pipe_dlg_param.vstartup_start; in dcn10_get_vstartup_for_pipe()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 357 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_helper_populate_phantom_dlg_params()
1730 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_calculate_dlg_params()
1762 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); in dcn32_calculate_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1203 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn20_calculate_dlg_params()
1208 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); in dcn20_calculate_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 687 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; in populate_subvp_cmd_vblank_pipe_info()
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