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Searched refs:pipe_plane (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_utils.h21 …ne_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);
A Ddml2_core_utils.c399 …ane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane) in dml2_core_utils_pipe_plane_mapping() argument
404 pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; in dml2_core_utils_pipe_plane_mapping()
409 pipe_plane[pipe_idx] = plane_idx; in dml2_core_utils_pipe_plane_mapping()
A Ddml2_core_dcn4_calcs.c222 pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; in dml_calc_pipe_plane_mapping()
227 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
247 unsigned int plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_is_phantom_pipe()
257 plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; \
10372 dml_calc_pipe_plane_mapping(cfg_support_info, mode_lib->mp.pipe_plane); in dml_core_mode_programming()
12150 unsigned int plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
12440 l->min_ttu_vblank = mode_lib->mp.MinTTUVBlank[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
12458 l->dst_y_prefetch = mode_lib->mp.dst_y_prefetch[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
12461 l->dst_y_per_vm_flip = mode_lib->mp.dst_y_per_vm_flip[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
12474 l->vratio_pre_l = mode_lib->mp.VRatioPrefetchY[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
[all …]
A Ddml2_core_shared_types.h834 …unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plan… member
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddisplay_mode_util.c759 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
771 if (plane_idx == mode_lib->mp.pipe_plane[i]) { in dml_get_pipe_idx()
782 void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane) in dml_calc_pipe_plane_mapping() argument
787 pipe_plane[k] = __DML_PIPE_NO_PLANE__; in dml_calc_pipe_plane_mapping()
792 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
A Ddisplay_mode_util.h73 …oid dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane);
A Ddml2_mall_phantom.c257 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0)… in assign_subvp_pipe()
623 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && in dml2_svp_validate_static_schedulability()
A Ddisplay_mode_core_structs.h1137 …dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to pla… member
A Ddisplay_mode_core.c8308 dml_calc_pipe_plane_mapping(&mode_lib->ms.cache_display_cfg.hw, mode_lib->mp.pipe_plane); in dml_core_mode_programming()
10203 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_is_phantom_pipe()
10211 plane_idx = mode_lib->mp.pipe_plane[surface_idx]; \
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1898 int pipe_plane = v->pipe_plane[pipe_idx]; in dcn20_validate_apply_pipe_split_flags() local
1905 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1907 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) in dcn20_validate_apply_pipe_split_flags()
1921 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; in dcn20_validate_apply_pipe_split_flags()
1925 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; in dcn20_validate_apply_pipe_split_flags()
1932 v->ODMCombineEnabled[pipe_plane] = in dcn20_validate_apply_pipe_split_flags()
1933 v->ODMCombineEnablePerState[vlevel][pipe_plane]; in dcn20_validate_apply_pipe_split_flags()
1935 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { in dcn20_validate_apply_pipe_split_flags()
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c134 which_plane = mode_lib->vba.pipe_plane[which_pipe]; \
264 if (plane_idx == mode_lib->vba.pipe_plane[i]) { in get_pipe_idx()
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_det_buffer_size_kbytes()
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_is_phantom_pipe()
545 mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes; in fetch_pipe_params()
789 mode_lib->vba.pipe_plane[k] = in fetch_pipe_params()
A Ddisplay_mode_vba.h589 unsigned int pipe_plane[DC__NUM_DPP__MAX]; member
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c520 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; in dcn32_set_phantom_stream_timing()
521 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; in dcn32_set_phantom_stream_timing()
636 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 … in dcn32_assign_subvp_pipe()
637 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && in dcn32_assign_subvp_pipe()
1065 …if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_… in subvp_validate_static_schedulability()
1252 odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] != in update_pipe_slice_table_with_split_flags()
1734 …lockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) in dcn32_calculate_dlg_params()
2043 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn32_apply_merge_split_flags_helper()
2226 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn32_internal_validate_bw()
3542 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0)… in dcn32_assign_fpo_vactive_candidate()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1708 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
1777 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn30_internal_validate_bw()
/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c830 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()

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