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Searched refs:pixel_clk (Results 1 – 21 of 21) sorted by relevance

/drivers/phy/mediatek/
A Dphy-mtk-hdmi-mt8195.c215 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; in mtk_hdmi_pll_calc() local
220 pixel_clk = rate; in mtk_hdmi_pll_calc()
221 tmds_clk = pixel_clk; in mtk_hdmi_pll_calc()
293 digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); in mtk_hdmi_pll_calc()
309 u32 pixel_clk = hdmi_phy->pll_rate; in mtk_hdmi_pll_drv_setting() local
311 tmds_clk = pixel_clk; in mtk_hdmi_pll_drv_setting()
329 } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { in mtk_hdmi_pll_drv_setting()
334 } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { in mtk_hdmi_pll_drv_setting()
/drivers/gpu/drm/bridge/synopsys/
A Ddw-hdmi-qp.c195 unsigned long pixel_clk, in dw_hdmi_qp_match_tmds_n_table() argument
202 if (pixel_clk == common_tmds_n_table[i].tmds) { in dw_hdmi_qp_match_tmds_n_table()
228 unsigned int pixel_clk) in dw_hdmi_qp_audio_math_diff() argument
230 u64 cts = mul_u32_u32(pixel_clk, n); in dw_hdmi_qp_audio_math_diff()
236 unsigned long pixel_clk, in dw_hdmi_qp_compute_n() argument
248 if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0) in dw_hdmi_qp_compute_n()
252 u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk); in dw_hdmi_qp_compute_n()
275 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate); in dw_hdmi_qp_find_n()
281 pixel_clk); in dw_hdmi_qp_find_n()
283 return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); in dw_hdmi_qp_find_n()
[all …]
A Ddw-mipi-dsi2.c325 u64 pixel_clk, ipi_clk, phy_hsclk; in dw_mipi_dsi2_phy_ratio_cfg() local
336 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; in dw_mipi_dsi2_phy_ratio_cfg()
337 ipi_clk = pixel_clk / 4; in dw_mipi_dsi2_phy_ratio_cfg()
457 u64 pixel_clk, phy_hs_clk; in dw_mipi_dsi2_ipi_set() local
478 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; in dw_mipi_dsi2_ipi_set()
483 hsa_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
487 hbp_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
491 hact_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
495 hline_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
A Ddw-hdmi.c574 if (pixel_clk == 25175000) in hdmi_compute_n()
576 else if (pixel_clk == 27027000) in hdmi_compute_n()
578 else if (pixel_clk == 74176000 || pixel_clk == 148352000) in hdmi_compute_n()
580 else if (pixel_clk == 297000000) in hdmi_compute_n()
588 if (pixel_clk == 25175000) in hdmi_compute_n()
590 else if (pixel_clk == 74176000) in hdmi_compute_n()
592 else if (pixel_clk == 148352000) in hdmi_compute_n()
602 if (pixel_clk == 25175000) in hdmi_compute_n()
604 else if (pixel_clk == 27027000) in hdmi_compute_n()
606 else if (pixel_clk == 74176000) in hdmi_compute_n()
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/drivers/gpu/drm/i915/display/
A Dintel_audio.c457 unsigned int h_active, h_total, hblank_delta, pixel_clk; in calc_hblank_early_prog() local
464 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; in calc_hblank_early_prog()
476 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) in calc_hblank_early_prog()
479 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; in calc_hblank_early_prog()
485 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
488 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), in calc_hblank_early_prog()
491 mul_u32_u32(64 * pixel_clk, 1000000)); in calc_hblank_early_prog()
501 unsigned int h_active, h_total, pixel_clk; in calc_samples_room() local
506 pixel_clk = crtc_state->hw.adjusted_mode.clock; in calc_samples_room()
510 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / in calc_samples_room()
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/drivers/media/platform/cadence/
A Dcdns-csi2rx.c129 struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; member
367 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
406 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
445 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
709 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); in csi2rx_get_resources()
710 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
712 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
A Dcdns-csi2tx.c108 struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; member
485 csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); in csi2tx_get_resources()
486 if (IS_ERR(csi2tx->pixel_clk[i])) { in csi2tx_get_resources()
489 return PTR_ERR(csi2tx->pixel_clk[i]); in csi2tx_get_resources()
/drivers/gpu/drm/mediatek/
A Dmtk_dpi.c75 struct clk *pixel_clk; member
512 clk_disable_unprepare(dpi->pixel_clk); in mtk_dpi_power_off()
536 ret = clk_prepare_enable(dpi->pixel_clk); in mtk_dpi_power_on()
592 clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); in mtk_dpi_set_pixel_clk()
594 clk_set_rate(dpi->pixel_clk, vm->pixelclock); in mtk_dpi_set_pixel_clk()
596 vm->pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_pixel_clk()
1308 dpi->pixel_clk = devm_clk_get(dev, "pixel"); in mtk_dpi_probe()
1309 if (IS_ERR(dpi->pixel_clk)) in mtk_dpi_probe()
1310 return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), in mtk_dpi_probe()
/drivers/gpu/drm/stm/
A Dltdc.c838 result = clk_round_rate(ldev->pixel_clk, target); in ltdc_crtc_mode_valid()
874 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { in ltdc_crtc_mode_fixup()
1874 clk_disable_unprepare(ldev->pixel_clk); in ltdc_suspend()
1884 ret = clk_prepare_enable(ldev->pixel_clk); in ltdc_resume()
1913 ldev->pixel_clk = devm_clk_get(dev, "lcd"); in ltdc_load()
1914 if (IS_ERR(ldev->pixel_clk)) { in ltdc_load()
1915 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) in ltdc_load()
1917 return PTR_ERR(ldev->pixel_clk); in ltdc_load()
1920 if (clk_prepare_enable(ldev->pixel_clk)) { in ltdc_load()
2035 clk_disable_unprepare(ldev->pixel_clk); in ltdc_load()
[all …]
A Dltdc.h46 struct clk *pixel_clk; /* lcd pixel clock */ member
/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c119 struct clk *pixel_clk; member
336 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); in dsi_clk_init()
337 if (IS_ERR(msm_host->pixel_clk)) in dsi_clk_init()
338 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), in dsi_clk_init()
396 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_6g()
450 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
466 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
501 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_v2()
532 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_v2()
555 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_disable_6g()
[all …]
/drivers/gpu/drm/msm/dp/
A Ddp_ctrl.c130 struct clk *pixel_clk; member
2173 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_process_phy_test_request()
2182 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_process_phy_test_request()
2483 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_on_stream()
2492 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_on_stream()
2553 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off_link_stream()
2607 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off()
2711 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); in msm_dp_ctrl_clk_init()
2712 if (IS_ERR(ctrl->pixel_clk)) in msm_dp_ctrl_clk_init()
2713 return PTR_ERR(ctrl->pixel_clk); in msm_dp_ctrl_clk_init()
/drivers/media/i2c/
A Dlt6911uxe.c88 u64 pixel_clk; member
139 bt->pixelclock = lt6911uxe->cur_mode.pixel_clk; in lt6911uxe_get_detected_timings()
286 lt6911uxe->cur_mode.pixel_clk = half_pix_clk * 2; in lt6911uxe_status_update()
/drivers/gpu/drm/amd/display/dc/inc/
A Dclock_source.h180 unsigned int pixel_clk,
/drivers/gpu/drm/aspeed/
A Daspeed_gfx_crtc.c93 clk_set_rate(priv->pixel_clk, m->crtc_clock * 1000); in aspeed_gfx_crtc_mode_set_nofb()
/drivers/gpu/drm/amd/display/include/
A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */ member
/drivers/gpu/drm/amd/display/dc/bios/
A Dcommand_table.c1542 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v2() local
1546 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v2()
1592 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v3() local
1596 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v3()
A Dbios_parser.c1246 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_2()
1364 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_3()
A Dbios_parser2.c1456 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.c1307 unsigned int pixel_clk, in dcn20_override_dp_pix_clk() argument
1313 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
/drivers/gpu/drm/i915/gvt/
A Dhandlers.c693 u64 pixel_clk = 0; in vgpu_update_refresh_rate() local
698 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); in vgpu_update_refresh_rate()
699 pixel_clk *= MSEC_PER_SEC; in vgpu_update_refresh_rate()
702 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()

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