Searched refs:pixel_rep (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/vc4/ |
| A D | vc4_crtc.c | 358 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1; in vc4_crtc_config_pv() local
386 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
388 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
392 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
394 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
399 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc); in vc4_crtc_config_pv()
454 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); in vc4_crtc_config_pv()
470 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
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| A D | vc4_hdmi.c | 1193 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc4_hdmi_set_timings() local
1219 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_set_timings()
1224 mode->hsync_end) * pixel_rep, in vc4_hdmi_set_timings()
1227 mode->hsync_start) * pixel_rep, in vc4_hdmi_set_timings()
1230 mode->hdisplay) * pixel_rep, in vc4_hdmi_set_timings()
1257 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc5_hdmi_set_timings() local
1263 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), in vc5_hdmi_set_timings()
1285 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc5_hdmi_set_timings()
1288 mode->hdisplay) * pixel_rep, in vc5_hdmi_set_timings()
1293 mode->hsync_end) * pixel_rep, in vc5_hdmi_set_timings()
[all …]
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| /drivers/video/fbdev/aty/ |
| A D | mach64_gx.c | 87 u8 pixel_rep; in aty_set_dac_514() member
117 aty_st_514(0x0a, tab[i].pixel_rep, par); /* Pixel Format */ in aty_set_dac_514()
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