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Searched refs:pl2 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/xe/
A Dxe_gt_throttle.c70 u32 pl2 = xe_gt_throttle_get_limit_reasons(gt) & POWER_LIMIT_2_MASK; in read_reason_pl2() local
72 return pl2; in read_reason_pl2()
144 bool pl2 = !!read_reason_pl2(gt); in reason_pl2_show() local
146 return sysfs_emit(buff, "%u\n", pl2); in reason_pl2_show()
/drivers/platform/x86/hp/
A Dhp-wmi.c161 u8 pl2; member
1637 static int victus_s_set_cpu_pl1_pl2(u8 pl1, u8 pl2) in victus_s_set_cpu_pl1_pl2() argument
1643 if (pl1 == HP_POWER_LIMIT_NO_CHANGE || pl2 == HP_POWER_LIMIT_NO_CHANGE) in victus_s_set_cpu_pl1_pl2()
1647 if (pl2 < pl1) in victus_s_set_cpu_pl1_pl2()
1651 power_limits.pl2 = pl2; in victus_s_set_cpu_pl1_pl2()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_hwmgr.c4707 const struct smu7_performance_level *pl2) in smu7_are_power_levels_equal() argument
4709 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()
4710 (pl1->engine_clock == pl2->engine_clock) && in smu7_are_power_levels_equal()
4711 (pl1->pcie_gen == pl2->pcie_gen) && in smu7_are_power_levels_equal()
4712 (pl1->pcie_lane == pl2->pcie_lane)); in smu7_are_power_levels_equal()
A Dvega10_hwmgr.c5023 const struct vega10_performance_level *pl2) in vega10_are_power_levels_equal() argument
5025 return ((pl1->soc_clock == pl2->soc_clock) && in vega10_are_power_levels_equal()
5026 (pl1->gfx_clock == pl2->gfx_clock) && in vega10_are_power_levels_equal()
5027 (pl1->mem_clock == pl2->mem_clock)); in vega10_are_power_levels_equal()

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