| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_state.c | 311 state->stream_status[i].plane_count = 0; in dc_state_destruct()
457 for (i = 0; i < status->plane_count; i++) in remove_mpc_combine_for_stream()
523 stream_status->plane_count++; in dc_state_add_plane()
565 if (i == stream_status->plane_count) { in dc_state_remove_plane()
570 stream_status->plane_count--; in dc_state_remove_plane()
573 for (; i < stream_status->plane_count; i++) in dc_state_remove_plane()
612 old_plane_count = stream_status->plane_count; in dc_state_rem_all_planes_for_stream()
628 int plane_count, in dc_state_add_all_planes_for_stream() argument
634 for (i = 0; i < plane_count; i++) in dc_state_add_all_planes_for_stream()
891 old_plane_count = stream_status->plane_count; in dc_state_rem_all_phantom_planes_for_stream()
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| A D | dc.c | 1273 for (i = 0; i < stream_status->plane_count; i++) { in dc_get_visual_confirm_for_stream()
2157 context->stream_status[i].plane_count, in dc_commit_state_no_check()
2224 context->stream_status[i].plane_count, in dc_commit_state_no_check()
2359 set[i].plane_count = status->plane_count; in dc_commit_streams()
2360 for (j = 0; j < status->plane_count; j++) in dc_commit_streams()
3339 for (i = 0; i < status->plane_count; i++) { in backup_planes_and_stream_state()
3355 for (i = 0; i < status->plane_count; i++) { in restore_planes_and_stream_state()
4522 if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) { in could_mpcc_tree_change_for_active_pipes()
4623 for (j = 0; j < stream_status->plane_count; j++) in force_vsync_flip_in_minimal_transition_context()
4704 for (i = 0; i < status->plane_count; i++) in initialize_empty_surface_updates()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_utils.c | 44 for (j = 0; j < state->stream_status[i].plane_count; j++) { in dml21_get_plane_id()
339 if (!main_stream_status || main_stream_status->plane_count == 0) in dml21_handle_phantom_streams_planes()
402 if (context->stream_status[i].plane_count == 0 || in dml21_build_fams2_programming()
435 static_base_state->stream_v1.base.num_planes = context->stream_status[i].plane_count; in dml21_build_fams2_programming()
439 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dml21_build_fams2_programming()
476 for (j = 0; j < phantom_status->plane_count; j++) { in dml21_build_fams2_programming()
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| A D | dml21_translation_helper.c | 999 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dml21_wrapper_get_plane_id()
1078 unsigned int plane_count = 0; in dml21_map_dc_state_into_dml_display_cfg() local
1112 if (context->stream_status[stream_index].plane_count == 0) { in dml21_map_dc_state_into_dml_display_cfg()
1118 …for (plane_index = 0; plane_index < context->stream_status[stream_index].plane_count; plane_index+… in dml21_map_dc_state_into_dml_display_cfg()
1139 plane_count++; in dml21_map_dc_state_into_dml_display_cfg()
1144 if (plane_count == 0) { in dml21_map_dc_state_into_dml_display_cfg()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 189 if (context->stream_status[i].plane_count > 1) in dcn32_mpo_in_use()
252 if (context->stream_status[i].plane_count > 1) in override_det_for_subvp()
334 if (context->stream_status[i].plane_count > 0) in dcn32_determine_det_override()
335 plane_segments = stream_segments / context->stream_status[i].plane_count; in dcn32_determine_det_override()
566 if (!fpo_candidate_stream || !fpo_stream_status || fpo_stream_status->plane_count == 0) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_dc_resource_mgmt.c | 69 for (j = 0; j < state->stream_status[i].plane_count; j++) { in get_plane_id()
934 for (i = 0; i < status->plane_count; i++) { in populate_mpc_factors_for_stream()
967 for (plane_idx = 0; plane_idx < status->plane_count; plane_idx++) in unmap_dc_pipes_for_stream()
996 for (plane_idx = 0; plane_idx < status->plane_count; plane_idx++) in map_dc_pipes_for_stream()
1115 if (state->stream_status[stream_index].plane_count == 0) { in dml2_map_dc_pipes()
1119 …for (plane_index = 0; plane_index < state->stream_status[stream_index].plane_count; plane_index++)… in dml2_map_dc_pipes()
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| A D | dml2_mall_phantom.c | 167 if (context->stream_status[i].plane_count > 1) in mpo_in_use()
828 old_plane_count = stream_status->plane_count; in remove_all_phantom_planes_for_stream()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_state.h | 71 int plane_count,
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| A D | dc_state_priv.h | 93 int plane_count,
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| A D | dc_stream.h | 58 int plane_count; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 614 unsigned int i, plane_count = 0; in dcn351_decide_zstate_support() local
618 plane_count++; in dcn351_decide_zstate_support()
622 if (context->stream_count == 0 || plane_count == 0) { in dcn351_decide_zstate_support()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 581 unsigned int i, plane_count = 0; in dcn35_decide_zstate_support() local
586 plane_count++; in dcn35_decide_zstate_support()
589 if (context->stream_count == 0 || plane_count == 0) { in dcn35_decide_zstate_support()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| A D | clk_mgr.c | 70 …tream->dpms_off || dc->is_switch_in_progress_dest || (stream_status && stream_status->plane_count)) in clk_mgr_helper_get_active_display_cnt()
90 total_plane_count += stream_status.plane_count; in clk_mgr_helper_get_active_plane_cnt()
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| /drivers/media/platform/amphion/ |
| A D | vpu_v4l2.c | 471 unsigned int *plane_count, in vpu_vb2_queue_setup() argument
481 if (*plane_count) { in vpu_vb2_queue_setup()
482 if (*plane_count != cur_fmt->mem_planes) in vpu_vb2_queue_setup()
495 *plane_count = cur_fmt->mem_planes; in vpu_vb2_queue_setup()
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| /drivers/media/platform/samsung/s5p-mfc/ |
| A D | s5p_mfc_dec.c | 937 unsigned int *plane_count, unsigned int psize[], in s5p_mfc_queue_setup() argument
949 *plane_count = 1; in s5p_mfc_queue_setup()
964 *plane_count = format->comp_planes; in s5p_mfc_queue_setup()
979 *buf_count, *plane_count); in s5p_mfc_queue_setup()
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| A D | s5p_mfc_enc.c | 2418 unsigned int *buf_count, unsigned int *plane_count, in s5p_mfc_queue_setup() argument
2431 *plane_count = ctx->dst_fmt->num_planes; in s5p_mfc_queue_setup()
2433 *plane_count = MFC_ENC_CAP_PLANE_COUNT; in s5p_mfc_queue_setup()
2442 *plane_count = ctx->src_fmt->num_planes; in s5p_mfc_queue_setup()
2444 *plane_count = MFC_ENC_OUT_PLANE_COUNT; in s5p_mfc_queue_setup()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 1163 if (context->stream_status[i].plane_count == 0) in dcn10_validate_global()
1166 if (context->stream_status[i].plane_count > 2) in dcn10_validate_global()
1169 if (context->stream_status[i].plane_count > 1) in dcn10_validate_global()
1172 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dcn10_validate_global()
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| /drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| A D | dce110_resource.c | 1053 if (context->stream_status[i].plane_count == 0) in dce110_validate_surface_sets()
1056 if (context->stream_status[i].plane_count > 2) in dce110_validate_surface_sets()
1059 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dce110_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| A D | dce100_resource.c | 870 if (context->stream_status[i].plane_count == 0) in dce100_validate_surface_sets()
873 if (context->stream_status[i].plane_count > 1) in dce100_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 1217 if ((dc->current_state->stream_status[i].plane_count) && in dcn401_check_no_memory_request_for_cab()
1299 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { in dcn401_apply_idle_power_optimizations()
2234 dc->current_state->stream_status[0].plane_count == 1 && in dcn401_program_front_end_for_ctx()
2235 context->stream_status[0].plane_count > 1) { in dcn401_program_front_end_for_ctx()
2362 if (dc->current_state->stream_status[0].plane_count == 1 && in dcn401_post_unlock_program_front_end()
2363 context->stream_status[0].plane_count > 1) { in dcn401_post_unlock_program_front_end()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
| A D | dml2_internal_shared_types.h | 760 int plane_count; member
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| /drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| A D | dce112_resource.c | 999 if (context->stream_status[i].plane_count == 0) in dce112_validate_surface_sets()
1002 if (context->stream_status[i].plane_count > 1) in dce112_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 897 if (context->stream_status[i].plane_count == 0) in dce60_validate_surface_sets()
900 if (context->stream_status[i].plane_count > 1) in dce60_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 903 if (context->stream_status[i].plane_count == 0) in dce80_validate_surface_sets()
906 if (context->stream_status[i].plane_count > 1) in dce80_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1060 int plane_count; in decide_zstate_support() local
1063 plane_count = 0; in decide_zstate_support()
1066 plane_count++; in decide_zstate_support()
1080 if (plane_count == 0) in decide_zstate_support()
1093 if (stream_status->plane_count > 1) in decide_zstate_support()
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