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Searched refs:plane_id (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_sprite_regs.h354 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) argument
355 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) argument
356 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) argument
362 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) argument
363 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) argument
364 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) argument
365 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) argument
366 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) argument
372 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) argument
373 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) argument
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A Dskl_universal_plane.c245 enum plane_id plane_id) in icl_is_nv12_y_plane() argument
687 enum plane_id plane_id = plane->id; in icl_program_input_csc() local
831 enum plane_id plane_id = plane->id; in skl_write_plane_wm() local
877 enum plane_id plane_id = plane->id; in skl_plane_disable_arm() local
905 enum plane_id plane_id = plane->id; in icl_plane_disable_arm() local
924 enum plane_id plane_id = plane->id; in skl_plane_get_hw_state() local
1355 enum plane_id plane_id = plane->id; in icl_plane_csc_load_black() local
1391 enum plane_id plane_id = plane->id; in skl_plane_update_noarm() local
1422 enum plane_id plane_id = plane->id; in skl_plane_update_arm() local
1535 enum plane_id plane_id = plane->id; in icl_plane_update_noarm() local
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A Dskl_universal_plane.h19 enum plane_id;
23 enum pipe pipe, enum plane_id plane_id);
39 enum plane_id plane_id);
41 bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id);
A Dintel_display_irq.c75 bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id);
77 enum plane_id plane_id; member
80 static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) in handle_plane_fault() argument
86 plane = intel_crtc_get_plane(crtc, plane_id); in handle_plane_fault()
112 if (handler->handle(crtc, handler->plane_id)) in intel_pipe_fault_irq_handler()
1078 static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) in handle_plane_ats_fault() argument
1089 static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) in handle_pipedmc_ats_fault() argument
1100 static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id) in handle_pipedmc_fault() argument
1150 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, },
1151 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, },
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A Dskl_watermark.c307 enum plane_id plane_id; in skl_crtc_can_enable_sagv() local
359 enum plane_id plane_id; in tgl_crtc_can_enable_sagv() local
713 enum plane_id plane_id; in skl_pipe_ddb_get_hw_state() local
1290 enum plane_id plane_id; in skl_total_relative_data_rate() local
1308 enum plane_id plane_id, in skl_plane_wm_level() argument
1423 enum plane_id plane_id; in skl_crtc_allocate_plane_ddb() local
2263 enum plane_id plane_id; in skl_max_wm0_lines() local
2323 enum plane_id plane_id; in skl_wm_check_vblank() local
2342 enum plane_id plane_id; in skl_wm_check_vblank() local
3009 enum plane_id plane_id; in skl_pipe_wm_get_hw_state() local
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A Dintel_sprite.c73 enum plane_id plane_id = plane->id; in chv_sprite_update_csc() local
111 intel_de_write_fw(display, SPCSCC01(plane_id), in chv_sprite_update_csc()
113 intel_de_write_fw(display, SPCSCC23(plane_id), in chv_sprite_update_csc()
115 intel_de_write_fw(display, SPCSCC45(plane_id), in chv_sprite_update_csc()
117 intel_de_write_fw(display, SPCSCC67(plane_id), in chv_sprite_update_csc()
146 enum plane_id plane_id = plane->id; in vlv_sprite_update_clrc() local
349 enum plane_id plane_id = plane->id; in vlv_sprite_update_gamma() local
374 enum plane_id plane_id = plane->id; in vlv_sprite_update_noarm() local
396 enum plane_id plane_id = plane->id; in vlv_sprite_update_arm() local
445 enum plane_id plane_id = plane->id; in vlv_sprite_disable_arm() local
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A Di9xx_wm.c1058 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local
1152 enum plane_id plane_id; in g4x_invalidate_wms() local
1196 enum plane_id plane_id; in _g4x_compute_pipe_wm() local
1289 enum plane_id plane_id; in g4x_compute_intermediate_wm() local
1557 enum plane_id plane_id; in vlv_compute_fifo() local
1634 enum plane_id plane_id; in vlv_invalidate_wms() local
1677 enum plane_id plane_id = plane->id; in vlv_raw_plane_wm_compute() local
1741 enum plane_id plane_id; in _vlv_compute_pipe_wm() local
1976 enum plane_id plane_id; in vlv_compute_intermediate_wm() local
3773 enum plane_id plane_id; in g4x_wm_get_hw_state() local
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A Dintel_dpt_common.c18 enum plane_id plane_id; in intel_dpt_configure() local
20 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_dpt_configure()
21 if (plane_id == PLANE_CURSOR) in intel_dpt_configure()
24 intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
A Dskl_watermark.h11 enum plane_id;
54 enum plane_id plane_id,
57 enum plane_id plane_id);
A Dintel_bw.c853 enum plane_id plane_id; in intel_bw_crtc_data_rate() local
855 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_bw_crtc_data_rate()
860 if (plane_id == PLANE_CURSOR) in intel_bw_crtc_data_rate()
863 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
1305 enum plane_id plane_id, in skl_plane_calc_dbuf_bw() argument
1319 dbuf_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
1328 enum plane_id plane_id; in skl_crtc_calc_dbuf_bw() local
1335 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_calc_dbuf_bw()
1340 if (plane_id == PLANE_CURSOR) in skl_crtc_calc_dbuf_bw()
1345 crtc_state->data_rate[plane_id]); in skl_crtc_calc_dbuf_bw()
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A Dintel_plane.h20 enum plane_id;
23 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id);
A Dintel_plane.c730 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) in intel_crtc_get_plane() argument
736 if (plane->id == plane_id) in intel_crtc_get_plane()
809 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit() local
812 !(*update_mask & BIT(plane_id))) in skl_next_plane_to_commit()
815 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
816 ddb, I915_MAX_PLANES, plane_id) || in skl_next_plane_to_commit()
817 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
818 ddb_y, I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
821 *update_mask &= ~BIT(plane_id); in skl_next_plane_to_commit()
822 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
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A Dintel_frontbuffer.h63 #define INTEL_FRONTBUFFER(pipe, plane_id) \ argument
64 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
A Dintel_fbc_regs.h66 #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) argument
A Dintel_cursor.c631 enum plane_id plane_id = plane->id; in skl_write_cursor_wm() local
635 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
640 skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); in skl_write_cursor_wm()
643 skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); in skl_write_cursor_wm()
646 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_cursor_wm()
/drivers/gpu/drm/kmb/
A Dkmb_plane.c72 int plane_id = kmb_plane->id; in check_pixel_format() local
98 int plane_id = kmb_plane->id; in kmb_plane_atomic_check() local
145 int plane_id = kmb_plane->id; in kmb_plane_atomic_disable() local
150 if (WARN_ON(plane_id >= KMB_MAX_PLANES)) in kmb_plane_atomic_disable()
153 switch (plane_id) { in kmb_plane_atomic_disable()
162 kmb->plane_status[plane_id].disable = true; in kmb_plane_atomic_disable()
305 unsigned char plane_id, in kmb_plane_set_alpha() argument
357 unsigned char plane_id; in kmb_plane_atomic_update() local
373 plane_id = kmb_plane->id; in kmb_plane_atomic_update()
464 config_csc(kmb, plane_id); in kmb_plane_atomic_update()
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A Dkmb_drv.c207 int plane_id, dma0_state, dma1_state; in handle_lcd_irq() local
223 for (plane_id = LAYER_0; in handle_lcd_irq()
224 plane_id < KMB_MAX_PLANES; plane_id++) { in handle_lcd_irq()
225 if (kmb->plane_status[plane_id].disable) { in handle_lcd_irq()
228 (plane_id), in handle_lcd_irq()
232 kmb->plane_status[plane_id].ctrl); in handle_lcd_irq()
247 kmb->plane_status[plane_id].disable = false; in handle_lcd_irq()
/drivers/gpu/drm/sti/
A Dsti_mixer.c239 int plane_id, depth = plane->drm_plane.state->normalized_zpos; in sti_mixer_set_plane_depth() local
245 plane_id = GAM_DEPTH_GDP0_ID; in sti_mixer_set_plane_depth()
248 plane_id = GAM_DEPTH_GDP1_ID; in sti_mixer_set_plane_depth()
251 plane_id = GAM_DEPTH_GDP2_ID; in sti_mixer_set_plane_depth()
254 plane_id = GAM_DEPTH_GDP3_ID; in sti_mixer_set_plane_depth()
257 plane_id = GAM_DEPTH_VID0_ID; in sti_mixer_set_plane_depth()
271 if ((val & mask) == plane_id << (3 * i)) in sti_mixer_set_plane_depth()
276 plane_id = plane_id << (3 * depth); in sti_mixer_set_plane_depth()
281 plane_id, mask); in sti_mixer_set_plane_depth()
284 val |= plane_id; in sti_mixer_set_plane_depth()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_dc_resource_mgmt.c64 if (!plane_id) in get_plane_id()
72 *plane_id = (i << 16) | j; in get_plane_id()
124 struct dc_state *state, unsigned int plane_id) in find_master_pipe_of_plane() argument
133 if (plane_id_assigned_to_pipe == plane_id) in find_master_pipe_of_plane()
649 unsigned int plane_id; in assign_pipes_to_plane() local
760 unsigned int plane_id; in map_pipes_for_plane() local
801 unsigned int plane_id; in get_target_mpc_factor() local
807 stream->stream_id, plane_idx, &plane_id); in get_target_mpc_factor()
833 stream->stream_id, plane_idx, &plane_id); in get_target_mpc_factor()
1045 unsigned int plane_id; in dml2_map_dc_pipes() local
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A Ddml2_utils.c205 static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) in find_dml_pipe_idx_by_plane_id() argument
209 …ane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) in find_dml_pipe_idx_by_plane_id()
217 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) in get_plane_id() argument
222 if (!plane_id) in get_plane_id()
230 *plane_id = (i << 16) | j; in get_plane_id()
281 unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id; in dml2_calculate_rq_and_dlg_params() local
307 …g.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) { in dml2_calculate_rq_and_dlg_params()
308 dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id); in dml2_calculate_rq_and_dlg_params()
513 unsigned int i = 0, dml_pipe_idx = 0, plane_id = 0; in dml2_verify_det_buffer_configuration() local
524 …_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id)) in dml2_verify_det_buffer_configuration()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_utils.h19 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id);
20 …plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);
45 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id);
A Ddml21_utils.c25 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) in dml21_find_dml_pipe_idx_by_plane_id() argument
29 …dx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) in dml21_find_dml_pipe_idx_by_plane_id()
36 …_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id) in dml21_get_plane_id() argument
40 if (!plane_id) in dml21_get_plane_id()
46 *plane_id = (i << 16) | j; in dml21_get_plane_id()
55 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id) in dml21_get_dc_plane_idx_from_plane_id() argument
57 return 0xffff & plane_id; in dml21_get_dc_plane_idx_from_plane_id()
/drivers/gpu/drm/i915/gvt/
A Ddmabuf.c257 int plane_id) in vgpu_get_plane_info() argument
265 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { in vgpu_get_plane_info()
295 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { in vgpu_get_plane_info()
317 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
/drivers/media/platform/nvidia/tegra-vde/
A Dh264.c674 unsigned int plane_id, in tegra_vde_validate_vb_size() argument
677 u64 offset = vb->planes[plane_id].data_offset; in tegra_vde_validate_vb_size()
680 if (offset + min_size > vb2_plane_size(vb, plane_id)) { in tegra_vde_validate_vb_size()
682 plane_id, vb2_plane_size(vb, plane_id), offset, min_size); in tegra_vde_validate_vb_size()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_trace.h651 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
655 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
659 __field( uint32_t, plane_id )
673 __entry->plane_id = plane_id;
689 __entry->crtc_id, __entry->plane_id, __entry->fb_id,

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