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Searched refs:plane_res (Results 1 – 25 of 47) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
299 (pipe_ctx->plane_res.xfm, &tbl_entry); in dce60_program_front_end_for_pipe()
310 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); in dce60_program_front_end_for_pipe()
329 pipe_ctx->plane_res.mi, in dce60_program_front_end_for_pipe()
373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe()
374 pipe_ctx->plane_res.scl_data.viewport.y, in dce60_program_front_end_for_pipe()
377 pipe_ctx->plane_res.scl_data.recout.x, in dce60_program_front_end_for_pipe()
378 pipe_ctx->plane_res.scl_data.recout.y); in dce60_program_front_end_for_pipe()
[all …]
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c1165 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios()
1166 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
1534 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1538 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1546 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1550 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1559 pipe_ctx->plane_res.xfm, in resource_build_scaling_params()
1565 pipe_ctx->plane_res.dpp, in resource_build_scaling_params()
1590 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; in resource_build_scaling_params()
1592 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; in resource_build_scaling_params()
[all …]
A Ddc_stream.c373 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
375 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
376 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
458 pipe_ctx->plane_res.hubp->mpcc_id); in dc_stream_program_cursor_position()
774 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
A Ddc_hw_sequencer.c338 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
395 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
850 …e[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence()
856 …ce[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence()
1034 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp()
1060 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale()
1238 hubp = pipe_ctx->plane_res.hubp; in hwss_wait_for_outstanding_hw_updates()
A Ddc_surface.c76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c412 switch (pipe->plane_res.scl_data.lb_params.depth) { in pipe_ctx_to_e2e_pipe_params()
949 + pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
951 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
955 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
958 - pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
961 + pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
963 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
967 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
970 - pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
973 + pipe->bottom_pipe->plane_res.scl_data.recout.width; in dcn_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c904 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn35_enable_plane()
907 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn35_enable_plane()
933 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn35_enable_plane()
971 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn35_plane_atomic_disable()
987 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn35_disable_plane()
1036 if (pipe_ctx->plane_res.hubp) in dcn35_calc_blocks_to_gate()
1039 if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp) in dcn35_calc_blocks_to_gate()
1154 cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp && in dcn35_calc_blocks_to_ungate()
1155 new_pipe->plane_res.hubp) in dcn35_calc_blocks_to_ungate()
1159 cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp && in dcn35_calc_blocks_to_ungate()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1496 pipe_ctx->plane_res.xfm, in program_scaler()
1514 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
2057 pipe_ctx->plane_res.mi, in dce110_set_displaymarks()
2066 pipe_ctx->plane_res.mi, in dce110_set_displaymarks()
2629 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); in program_gamut_remap()
2640 pipe_ctx->plane_res.mi, in update_plane_addr()
2656 pipe_ctx->plane_res.mi); in dce110_update_pending_status()
2659 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; in dce110_update_pending_status()
2967 pipe_ctx->plane_res.mi, in dce110_program_front_end_for_pipe()
3041 pipe_ctx->plane_res.mi, in dce110_apply_ctx_for_surface()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c397 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
728 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
733 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn20_plane_atomic_disable()
749 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn20_disable_plane()
1313 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn20_enable_plane()
1316 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn20_enable_plane()
1376 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn20_enable_plane()
1592 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn20_detect_pipe_changes()
1597 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) in dcn20_detect_pipe_changes()
1774 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn20_update_dchubp_dpp()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1507 pipe_ctx->plane_res.dpp, in dcn10_plane_atomic_disable()
1508 pipe_ctx->plane_res.hubp); in dcn10_plane_atomic_disable()
1512 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn10_plane_atomic_disable()
1523 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn10_disable_plane()
1983 pipe_ctx->plane_res.hubp, in dcn10_update_plane_addr()
2712 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn10_enable_plane()
2730 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn10_enable_plane()
2755 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); in dcn10_program_gamut_remap()
2785 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); in dcn10_set_csc_adjustment_rgb_mpo_fix()
2814 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); in dcn10_program_output_csc()
[all …]
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c98 populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format); in translate_SPL_in_params_from_pipe_ctx()
139 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx()
197 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
198 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx()
218 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx()
220 …populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->rat… in translate_SPL_out_params_to_pipe_ctx()
222 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewp… in translate_SPL_out_params_to_pipe_ctx()
224 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->vie… in translate_SPL_out_params_to_pipe_ctx()
226 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx()
228 populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); in translate_SPL_out_params_to_pipe_ctx()
A Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c150 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
313 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
314 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
315 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
346 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
380 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect()
381 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
424 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_update_mpcc()
563 pipe_ctx->plane_res.hubp, attributes); in dcn201_set_cursor_attribute()
565 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c1063 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn401_set_cursor_position()
1458 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, in dcn401_optimize_bandwidth()
1661 dpp_pipe->plane_res.hubp && in dcn401_wait_for_det_buffer_update_under_otg_master()
1757 wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); in dcn401_perform_3dlut_wa_unlock()
1766 wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); in dcn401_perform_3dlut_wa_unlock()
2236 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); in dcn401_program_front_end_for_ctx()
2420 pipe_ctx->plane_res.hubp, in dcn401_update_bandwidth()
2546 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn401_detect_pipe_changes()
2551 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) in dcn401_detect_pipe_changes()
2555 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn401_detect_pipe_changes()
[all …]
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_trace.h386 const struct plane_resource *plane_res,
388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1490 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1491 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1492 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1494 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1546 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1548 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1783 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); in dcn20_merge_pipes_for_validate()
1808 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); in dcn20_merge_pipes_for_validate()
2164 sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx]; in dcn20_acquire_free_pipe_for_layer()
2165 sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx]; in dcn20_acquire_free_pipe_for_layer()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c234 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
256 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
257 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
318 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
358 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_program_gamut_remap()
372 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, in dcn30_program_gamut_remap()
394 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
608 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
885 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c62 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + in dml2_helper_calculate_num_ways_for_subvp()
63 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + in dml2_helper_calculate_num_ways_for_subvp()
64 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); in dml2_helper_calculate_num_ways_for_subvp()
126 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in merge_pipes_for_subvp()
140 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in merge_pipes_for_subvp()
A Ddml2_utils.c273 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
274 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
275 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
276 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
335 …context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&… in dml2_calculate_rq_and_dlg_params()
336 …w_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz) in dml2_calculate_rq_and_dlg_params()
337 …context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.… in dml2_calculate_rq_and_dlg_params()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
133 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
147 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
A Ddcn32_resource.c2759 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2760 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2761 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2819 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2820 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2821 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2849 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2850 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2851 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2852 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddmub_psr.c341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
343 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
443 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
479 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts()
480 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts()
527 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func()
564 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func()
608 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_force_pstate()
628 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_force_pstate()
673 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_mall_sel()
733 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_program_mall_pipe_config()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
170 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1533 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1534 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1535 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1536 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1537 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1538 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1743 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
1758 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()

Completed in 91 milliseconds

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