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Searched refs:plane_state (Results 1 – 25 of 185) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
A Ddc_surface.c42 plane_state->ctx = ctx; in dc_plane_construct()
76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
88 struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state), in dc_create_plane_state() local
91 if (NULL == plane_state) in dc_create_plane_state()
97 return plane_state; in dc_create_plane_state()
119 if (!plane_state || in dc_plane_get_status()
120 !plane_state->ctx || in dc_plane_get_status()
137 if (pipe_ctx->plane_state != plane_state) in dc_plane_get_status()
152 if (pipe_ctx->plane_state != plane_state) in dc_plane_get_status()
171 kvfree(plane_state); in dc_plane_state_free()
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A Ddc_hw_sequencer.c590 if (!pipe_ctx->plane_state->dcc.enable) { in get_dcc_visual_confirm_color()
785 if (current_mpc_pipe->plane_state) { in hwss_build_fast_sequence()
818 …ence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state; in hwss_build_fast_sequence()
1035 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in hwss_setup_dpp() local
1037 if (!plane_state) in hwss_setup_dpp()
1043 plane_state->format, in hwss_setup_dpp()
1045 plane_state->input_csc_color_matrix, in hwss_setup_dpp()
1046 plane_state->color_space, in hwss_setup_dpp()
1052 plane_state->color_space, in hwss_setup_dpp()
1053 plane_state->cursor_csc_color_matrix); in hwss_setup_dpp()
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/drivers/gpu/drm/i915/display/
A Dintel_cursor.c113 plane_state, 0); in intel_cursor_check_surface()
169 plane_state->uapi.src = src; in intel_check_cursor()
170 plane_state->uapi.dst = dst; in intel_check_cursor()
277 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); in i845_check_cursor()
291 if (plane_state && plane_state->uapi.visible) { in i845_cursor_update_arm()
295 cntl = plane_state->ctl | in i845_cursor_update_arm()
530 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { in i9xx_check_cursor()
537 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); in i9xx_check_cursor()
668 if (plane_state && plane_state->uapi.visible) { in i9xx_cursor_update_arm()
672 cntl = plane_state->ctl | in i9xx_cursor_update_arm()
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A Dintel_sprite.c375 int crtc_x = plane_state->uapi.dst.x1; in vlv_sprite_update_noarm()
376 int crtc_y = plane_state->uapi.dst.y1; in vlv_sprite_update_noarm()
408 chv_sprite_update_csc(plane_state); in vlv_sprite_update_arm()
434 vlv_sprite_update_clrc(plane_state); in vlv_sprite_update_arm()
435 vlv_sprite_update_gamma(plane_state); in vlv_sprite_update_arm()
939 &plane_state->uapi.dst, in g4x_sprite_min_cdclk()
1378 if (!plane_state->uapi.visible) in g4x_sprite_check()
1390 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); in g4x_sprite_check()
1392 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); in g4x_sprite_check()
1435 if (!plane_state->uapi.visible) in vlv_sprite_check()
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A Dskl_universal_plane.c1296 if (plane_state->decrypt) in skl_plane_surf()
1378 if (plane_state->planar_linked_plane && !plane_state->is_y_plane) in icl_plane_color_plane()
1944 plane_state, in skl_check_main_ccs_coordinates()
2124 plane_state, in skl_check_nv12_aux_surface()
2135 plane_state, in skl_check_nv12_aux_surface()
2189 plane_state, in skl_check_ccs_aux_surface()
2269 !plane_state->decrypt; in check_protection()
2352 clip_damage(plane_state); in skl_plane_check()
2366 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); in skl_plane_check()
2370 plane_state); in skl_plane_check()
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A Dintel_fbc.c1311 WARN_ON(plane_state->no_fbc_reason); in intel_fbc_update_state()
1367 return !plane_state->no_fbc_reason && in intel_fbc_is_ok()
1368 intel_fbc_is_fence_ok(plane_state) && in intel_fbc_is_ok()
1369 intel_fbc_is_cfb_ok(plane_state); in intel_fbc_is_ok()
1386 !intel_fbc_is_ok(plane_state)) { in __intel_fbc_prepare_dirty_rect()
1458 if (!plane_state->uapi.visible) { in intel_fbc_check_plane()
1516 if (!tiling_is_valid(plane_state)) { in intel_fbc_check_plane()
1526 if (!stride_is_valid(plane_state)) { in intel_fbc_check_plane()
1581 plane_state->no_fbc_reason = NULL; in intel_fbc_check_plane()
1860 if (intel_fbc_is_ok(plane_state)) { in __intel_fbc_enable()
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A Dintel_plane.c69 memset(plane_state, 0, sizeof(*plane_state)); in intel_plane_state_reset()
73 plane_state->scaler_id = -1; in intel_plane_state_reset()
85 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL); in intel_plane_alloc()
86 if (!plane_state) { in intel_plane_alloc()
169 if (plane_state->hw.fb) in intel_plane_destroy_state()
171 kfree(plane_state); in intel_plane_destroy_state()
358 if (plane_state->hw.fb) in intel_plane_clear_hw_state()
361 memset(&plane_state->hw, 0, sizeof(plane_state->hw)); in intel_plane_clear_hw_state()
398 if (plane_state->hw.fb) in intel_plane_copy_uapi_to_hw_state()
421 if (plane_state->hw.fb) in intel_plane_copy_hw_state()
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A Dintel_fb_pin.c256 &plane_state->view, in intel_plane_fb_vtd_guard()
257 plane_state->hw.rotation); in intel_plane_fb_vtd_guard()
265 to_intel_framebuffer(plane_state->hw.fb); in intel_plane_pin_fb()
273 intel_plane_uses_fence(plane_state), in intel_plane_pin_fb()
274 &plane_state->flags); in intel_plane_pin_fb()
278 plane_state->ggtt_vma = vma; in intel_plane_pin_fb()
298 plane_state->ggtt_vma = vma; in intel_plane_pin_fb()
301 alignment, &plane_state->flags, in intel_plane_pin_fb()
305 plane_state->ggtt_vma = NULL; in intel_plane_pin_fb()
309 plane_state->dpt_vma = vma; in intel_plane_pin_fb()
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A Di9xx_plane.c243 if (!plane_state->uapi.visible) in i9xx_check_plane_surface()
247 src_x = plane_state->uapi.src.x1 >> 16; in i9xx_check_plane_surface()
248 src_y = plane_state->uapi.src.y1 >> 16; in i9xx_check_plane_surface()
262 plane_state, 0); in i9xx_check_plane_surface()
351 if (!plane_state->uapi.visible) in i9xx_plane_check()
358 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); in i9xx_plane_check()
440 int crtc_x = plane_state->uapi.dst.x1; in i9xx_plane_update_noarm()
441 int crtc_y = plane_state->uapi.dst.y1; in i9xx_plane_update_noarm()
483 int crtc_x = plane_state->uapi.dst.x1; in i9xx_plane_update_arm()
484 int crtc_y = plane_state->uapi.dst.y1; in i9xx_plane_update_arm()
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A Dintel_plane_initial.c43 if (!plane_state->ggtt_vma) in intel_reuse_initial_plane_obj()
47 *fb = plane_state->hw.fb; in intel_reuse_initial_plane_obj()
48 *vma = plane_state->ggtt_vma; in intel_reuse_initial_plane_obj()
355 plane_state->uapi.rotation, &plane_state->view); in intel_find_initial_plane_obj()
363 plane_state->uapi.src_x = 0; in intel_find_initial_plane_obj()
364 plane_state->uapi.src_y = 0; in intel_find_initial_plane_obj()
368 plane_state->uapi.crtc_x = 0; in intel_find_initial_plane_obj()
369 plane_state->uapi.crtc_y = 0; in intel_find_initial_plane_obj()
370 plane_state->uapi.crtc_w = fb->width; in intel_find_initial_plane_obj()
376 plane_state->uapi.fb = fb; in intel_find_initial_plane_obj()
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A Dskl_scaler.c297 &plane_state->scaler_id, in skl_update_scaler_plane()
382 if (plane_state && plane_state->hw.fb && in intel_atomic_setup_scaler()
398 plane_state->planar_linked_plane; in intel_atomic_setup_scaler()
421 if (plane_state && plane_state->hw.fb) { in intel_atomic_setup_scaler()
522 struct intel_plane_state *plane_state; in setup_plane_scaler() local
539 if (IS_ERR(plane_state)) in setup_plane_scaler()
540 return PTR_ERR(plane_state); in setup_plane_scaler()
545 plane_state, &plane_state->scaler_id); in setup_plane_scaler()
804 &plane_state->uapi.dst, in skl_program_plane_scaler()
807 &plane_state->uapi.dst, in skl_program_plane_scaler()
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A Dintel_plane.h30 const struct intel_plane_state *plane_state);
33 const struct intel_plane_state *plane_state,
35 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
38 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
43 const struct intel_plane_state *plane_state,
48 const struct intel_plane_state *plane_state);
52 const struct intel_plane_state *plane_state);
75 int intel_plane_check_clipping(struct intel_plane_state *plane_state,
79 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
81 struct intel_plane_state *plane_state);
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A Dintel_sprite_uapi.c16 static void intel_plane_set_ckey(struct intel_plane_state *plane_state, in intel_plane_set_ckey() argument
19 struct intel_display *display = to_intel_display(plane_state); in intel_plane_set_ckey()
20 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_set_ckey()
21 struct drm_intel_sprite_colorkey *key = &plane_state->ckey; in intel_plane_set_ckey()
48 struct drm_plane_state *plane_state; in intel_sprite_set_colorkey_ioctl() local
92 plane_state = drm_atomic_get_plane_state(state, plane); in intel_sprite_set_colorkey_ioctl()
93 ret = PTR_ERR_OR_ZERO(plane_state); in intel_sprite_set_colorkey_ioctl()
95 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); in intel_sprite_set_colorkey_ioctl()
106 plane_state = drm_atomic_get_plane_state(state, in intel_sprite_set_colorkey_ioctl()
108 ret = PTR_ERR_OR_ZERO(plane_state); in intel_sprite_set_colorkey_ioctl()
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/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c101 if (!pipe_ctx->plane_state) in dce60_should_enable_fbc()
188 if (!pipe_ctx->plane_state->visible) in dce60_program_surface_visibility()
274 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dce60_program_front_end_for_pipe() local
318 plane_state->format, in dce60_program_front_end_for_pipe()
319 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
320 &plane_state->plane_size, in dce60_program_front_end_for_pipe()
321 plane_state->rotation, in dce60_program_front_end_for_pipe()
330 plane_state->format, in dce60_program_front_end_for_pipe()
331 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
332 plane_state->rotation); in dce60_program_front_end_for_pipe()
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/drivers/gpu/drm/
A Ddrm_gem_atomic_helper.c222 struct drm_plane_state *plane_state = plane->state; in __drm_gem_duplicate_shadow_plane_state() local
224 to_drm_shadow_plane_state(plane_state); in __drm_gem_duplicate_shadow_plane_state()
253 struct drm_plane_state *plane_state = plane->state; in drm_gem_duplicate_shadow_plane_state() local
256 if (!plane_state) in drm_gem_duplicate_shadow_plane_state()
292 struct drm_plane_state *plane_state) in drm_gem_destroy_shadow_plane_state() argument
295 to_drm_shadow_plane_state(plane_state); in drm_gem_destroy_shadow_plane_state()
361 struct drm_framebuffer *fb = plane_state->fb; in drm_gem_begin_shadow_fb_access()
383 struct drm_framebuffer *fb = plane_state->fb; in drm_gem_end_shadow_fb_access()
406 struct drm_plane_state *plane_state) in drm_gem_simple_kms_begin_shadow_fb_access() argument
424 struct drm_plane_state *plane_state) in drm_gem_simple_kms_end_shadow_fb_access() argument
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/drivers/gpu/drm/amd/display/dc/basics/
A Ddc_common.c55 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_lower_pipe_tree_visible()
64 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_upper_pipe_tree_visible()
73 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_pipe_tree_visible()
83 const struct dc_plane_state *plane_state) in build_prescale_params() argument
85 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN in build_prescale_params()
86 && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID in build_prescale_params()
87 && plane_state->input_csc_color_matrix.enable_adjustment in build_prescale_params()
88 && plane_state->coeff_reduction_factor.value != 0) { in build_prescale_params()
90 dc_fixpt_mul(plane_state->coeff_reduction_factor, in build_prescale_params()
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c78 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; in translate_SPL_in_params_from_pipe_ctx() local
84 switch (plane_state->ctx->dce_version) { in translate_SPL_in_params_from_pipe_ctx()
108 spl_in->basic_in.rotation = (enum spl_rotation_angle)plane_state->rotation; in translate_SPL_in_params_from_pipe_ctx()
110 populate_splrect_from_rect(&spl_in->basic_in.src_rect, &plane_state->src_rect); in translate_SPL_in_params_from_pipe_ctx()
112 populate_splrect_from_rect(&spl_in->basic_in.dst_rect, &plane_state->dst_rect); in translate_SPL_in_params_from_pipe_ctx()
114 spl_in->basic_in.horizontal_mirror = plane_state->horizontal_mirror; in translate_SPL_in_params_from_pipe_ctx()
175 } else if (!plane_state->adaptive_sharpness_en) { in translate_SPL_in_params_from_pipe_ctx()
180 spl_in->adaptive_sharpness.sharpness_level = plane_state->sharpness_level; in translate_SPL_in_params_from_pipe_ctx()
187 spl_in->lls_pref = plane_state->linear_light_scaling; in translate_SPL_in_params_from_pipe_ctx()
192 spl_in->basic_in.cositing = plane_state->cositing; in translate_SPL_in_params_from_pipe_ctx()
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/drivers/gpu/drm/xe/display/
A Dxe_plane_initial.c62 if (!plane_state->ggtt_vma) in intel_reuse_initial_plane_obj()
66 *fb = plane_state->hw.fb; in intel_reuse_initial_plane_obj()
229 plane_state->uapi.rotation, &plane_state->view); in intel_find_initial_plane_obj()
236 plane_state->ggtt_vma = vma; in intel_find_initial_plane_obj()
237 plane_state->uapi.src_x = 0; in intel_find_initial_plane_obj()
238 plane_state->uapi.src_y = 0; in intel_find_initial_plane_obj()
242 plane_state->uapi.crtc_x = 0; in intel_find_initial_plane_obj()
243 plane_state->uapi.crtc_y = 0; in intel_find_initial_plane_obj()
244 plane_state->uapi.crtc_w = fb->width; in intel_find_initial_plane_obj()
247 plane_state->uapi.fb = fb; in intel_find_initial_plane_obj()
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/drivers/gpu/drm/tests/
A Ddrm_plane_helper_test.c88 KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0, in check_src_eq()
90 plane_state->src.x1, DRM_RECT_FP_ARG(&plane_state->src)); in check_src_eq()
92 KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0, in check_src_eq()
94 plane_state->src.y1, DRM_RECT_FP_ARG(&plane_state->src)); in check_src_eq()
98 DRM_RECT_FP_ARG(&plane_state->src), DRM_RECT_FP_ARG(&expected)); in check_src_eq()
109 DRM_RECT_ARG(&plane_state->dst), DRM_RECT_ARG(&expected)); in check_crtc_eq()
115 struct drm_plane_state *plane_state = test->priv; in drm_test_check_plane_state() local
118 drm_atomic_helper_check_plane_state(plane_state, &crtc_state, in drm_test_check_plane_state()
123 KUNIT_EXPECT_TRUE(test, plane_state->visible); in drm_test_check_plane_state()
257 struct drm_plane_state *plane_state = test->priv; in drm_test_check_invalid_plane_state() local
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/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c1512 if (!old_pipe->plane_state && !new_pipe->plane_state) in dcn20_detect_pipe_changes()
1515 if (!old_pipe->plane_state && new_pipe->plane_state) { in dcn20_detect_pipe_changes()
1552 if (old_pipe->plane_state && !new_pipe->plane_state) { in dcn20_detect_pipe_changes()
1558 if (old_pipe->plane_state != new_pipe->plane_state) { in dcn20_detect_pipe_changes()
1679 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn20_update_dchubp_dpp() local
2012 if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) { in dcn20_program_pipe()
2698 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo() local
2700 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
2727 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn20_update_plane_addr() local
2742 plane_state->status.requested_address = plane_state->address; in dcn20_update_plane_addr()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c59 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo() local
61 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
69 plane_state->address.grph_stereo.left_addr = in patch_address_for_sbs_tb_stereo()
137 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn201_update_plane_addr() local
141 if (plane_state == NULL) in dcn201_update_plane_addr()
144 uma = plane_state->address; in dcn201_update_plane_addr()
152 plane_state->flip_immediate); in dcn201_update_plane_addr()
154 plane_state->status.requested_address = plane_state->address; in dcn201_update_plane_addr()
156 if (plane_state->flip_immediate) in dcn201_update_plane_addr()
157 plane_state->status.current_address = plane_state->address; in dcn201_update_plane_addr()
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/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c86 if (pipe->plane_state->dcc.enable) in dml2_helper_calculate_num_ways_for_subvp()
120 pipe->plane_state = NULL; in merge_pipes_for_subvp()
128 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in merge_pipes_for_subvp()
138 pipe->plane_state = NULL; in merge_pipes_for_subvp()
156 if (!pipe->plane_state) in all_pipes_have_stream_and_plane()
255 if (pipe->plane_state && !pipe->top_pipe && in assign_subvp_pipe()
616 if (pipe->plane_state && !pipe->top_pipe && in dml2_svp_validate_static_schedulability()
746 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) { in enable_phantom_plane()
752 curr_pipe->plane_state); in enable_phantom_plane()
861 if (pipe->plane_state) { in dml2_svp_remove_all_phantom_pipes()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c239 (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) || in dcn10_lock_all_pipes()
1946 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo() local
1948 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
1975 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn10_update_plane_addr() local
1987 plane_state->status.requested_address = plane_state->address; in dcn10_update_plane_addr()
1990 plane_state->status.current_address = plane_state->address; in dcn10_update_plane_addr()
2767 if (top->plane_state && top->plane_state->layer_index == 0 && !top->plane_state->global_alpha) in dcn10_is_rear_mpo_fix_required()
2829 plane_state->format, in dcn10_update_dpp()
2950 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn10_update_dchubp_dpp() local
3091 &plane_state->dcc, in dcn10_update_dchubp_dpp()
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/drivers/gpu/drm/mediatek/
A Dmtk_crtc.c300 struct mtk_plane_state *plane_state; in ddp_cmdq_cb() local
304 plane_state->pending.config = false; in ddp_cmdq_cb()
412 struct mtk_plane_state *plane_state; in mtk_crtc_ddp_hw_init() local
419 plane_state->pending.enable = false; in mtk_crtc_ddp_hw_init()
423 plane_state, NULL); in mtk_crtc_ddp_hw_init()
509 if (!plane_state->pending.config) in mtk_crtc_ddp_config()
516 plane_state, in mtk_crtc_ddp_config()
540 plane_state, in mtk_crtc_ddp_config()
576 if (plane_state->pending.dirty) { in mtk_crtc_update_config()
742 memcpy(mtk_plane_state, plane_state, sizeof(*plane_state)); in mtk_crtc_plane_disable()
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/drivers/gpu/drm/ast/
A Dast_cursor.c189 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); in ast_cursor_plane_helper_atomic_update() local
191 struct drm_framebuffer *fb = plane_state->fb; in ast_cursor_plane_helper_atomic_update()
207 if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) { in ast_cursor_plane_helper_atomic_update()
238 writel(plane_state->crtc_x, sig + AST_HWC_SIGNATURE_X); in ast_cursor_plane_helper_atomic_update()
239 writel(plane_state->crtc_y, sig + AST_HWC_SIGNATURE_Y); in ast_cursor_plane_helper_atomic_update()
244 if (plane_state->crtc_x < 0) { in ast_cursor_plane_helper_atomic_update()
245 x_offset = (-plane_state->crtc_x) + offset_x; in ast_cursor_plane_helper_atomic_update()
249 x = plane_state->crtc_x; in ast_cursor_plane_helper_atomic_update()
251 if (plane_state->crtc_y < 0) { in ast_cursor_plane_helper_atomic_update()
252 y_offset = (-plane_state->crtc_y) + offset_y; in ast_cursor_plane_helper_atomic_update()
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