Searched refs:pll0 (Results 1 – 9 of 9) sorted by relevance
| /drivers/bcma/ |
| A D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
374 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
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| /drivers/gpu/drm/tegra/ |
| A D | hdmi.c | 44 u32 pll0; member
140 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
173 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
219 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
237 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
256 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
275 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
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| A D | sor.c | 367 unsigned int pll0; member
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
3284 .pll0 = 0x17,
3456 .pll0 = 0x17,
3517 .pll0 = 0x163,
[all …]
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| /drivers/clk/mxs/ |
| A D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_dpll_mgr.h | 208 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| A D | intel_dpll_mgr.c | 2075 PORT_PLL_M2_INT_MASK, hw_state->pll0); in bxt_ddi_pll_enable()
2193 hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2194 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2337 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2370 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2466 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2479 a->pll0 == b->pll0 && in bxt_compare_hw_state()
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| /drivers/phy/ti/ |
| A D | Kconfig | 49 three clock selects (pll0, pll1, dig) and resets for each of the
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| /drivers/clk/qcom/ |
| A D | gcc-mdm9615.c | 47 static struct clk_pll pll0 = { variable
69 &pll0.clkr.hw,
1615 [PLL0] = &pll0.clkr,
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| A D | gcc-ipq806x.c | 32 static struct clk_pll pll0 = { variable
54 &pll0.clkr.hw,
3067 [PLL0] = &pll0.clkr,
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Completed in 47 milliseconds