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Searched refs:pll1 (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/drivers/gpu/drm/nouveau/dispnv04/
A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
/drivers/gpu/drm/hisilicon/hibmc/
A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
/drivers/clk/spacemit/
A Dccu-k1.c64 CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1);
65 CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1);
66 CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1);
67 CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
68 CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
69 CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
70 CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
72 CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1);
73 CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1);
75 CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1);
[all …]
/drivers/gpu/drm/tegra/
A Dhdmi.c45 u32 pll1; member
143 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
158 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
176 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
204 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
239 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
258 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
277 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
318 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
[all …]
A Dsor.c368 unsigned int pll1; member
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
3285 .pll1 = 0x18,
3457 .pll1 = 0x18,
3518 .pll1 = 0x164,
[all …]
/drivers/clk/
A Dclk-ep93xx.c596 struct clk_hw *hw, *pll1; in ep93xx_plls_init() local
607 pll1 = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll1", &xtali, in ep93xx_plls_init()
609 if (IS_ERR(pll1)) in ep93xx_plls_init()
610 return PTR_ERR(pll1); in ep93xx_plls_init()
612 priv->fixed[EP93XX_CLK_PLL1] = pll1; in ep93xx_plls_init()
619 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, 1, clk_f_div); in ep93xx_plls_init()
625 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, 1, clk_h_div); in ep93xx_plls_init()
A Dclk-k210.c1002 struct k210_pll pll1; in k210_clk_early_init() local
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
1009 k210_pll_enable_hw(regs, &pll1); in k210_clk_early_init()
/drivers/media/i2c/
A Dov7251.c110 const struct ov7251_pll1_cfg *pll1[]; member
219 .pll1 = {
227 .pll1 = {
816 configs->pll1[ov7251->link_freq_idx]->pre_div); in ov7251_pll_configure()
821 configs->pll1[ov7251->link_freq_idx]->mult); in ov7251_pll_configure()
825 configs->pll1[ov7251->link_freq_idx]->div); in ov7251_pll_configure()
830 configs->pll1[ov7251->link_freq_idx]->pix_div); in ov7251_pll_configure()
835 configs->pll1[ov7251->link_freq_idx]->mipi_div); in ov7251_pll_configure()
/drivers/clk/mxs/
A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.h208 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
A Dintel_dpll_mgr.c2079 PORT_PLL_N_MASK, hw_state->pll1); in bxt_ddi_pll_enable()
2196 hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2197 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2338 hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
2374 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1); in bxt_ddi_pll_get_freq()
2466 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2480 a->pll1 == b->pll1 && in bxt_compare_hw_state()
/drivers/phy/ti/
A DKconfig49 three clock selects (pll0, pll1, dig) and resets for each of the

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