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Searched refs:pll2 (Results 1 – 12 of 12) sorted by relevance

/drivers/mfd/
A Dsm501.c121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
167 fmt_freq(pll2), sdclk0, sdclk1); in sm501_dump_clk()
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/drivers/gpu/drm/hisilicon/hibmc/
A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
300 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
316 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
323 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/drivers/media/i2c/
A Dov7251.c109 const struct ov7251_pll2_cfg *pll2; member
218 .pll2 = &ov7251_pll2_cfg_19_2_mhz,
226 .pll2 = &ov7251_pll2_cfg_24_mhz,
840 configs->pll2->pre_div); in ov7251_pll_configure()
845 configs->pll2->mult); in ov7251_pll_configure()
850 configs->pll2->div); in ov7251_pll_configure()
855 configs->pll2->sys_div); in ov7251_pll_configure()
860 configs->pll2->adc_div); in ov7251_pll_configure()
/drivers/gpu/drm/tegra/
A Dsor.c369 unsigned int pll2; member
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
3286 .pll2 = 0x19,
3458 .pll2 = 0x19,
3519 .pll2 = 0x165,
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/drivers/clk/spacemit/
A Dccu-k1.c59 CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
79 CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1);
80 CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1);
81 CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1);
82 CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1);
83 CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1);
84 CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1);
85 CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1);
86 CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1);
683 [CLK_PLL2] = &pll2.common.hw,
/drivers/clk/mxs/
A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
/drivers/clk/sunxi/
A DMakefile12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.h208 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
A Dintel_dpll_mgr.c2083 PORT_PLL_M2_FRAC_MASK, hw_state->pll2); in bxt_ddi_pll_enable()
2199 hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2200 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2339 hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff); in bxt_ddi_set_dpll_hw_state()
2373 hw_state->pll2); in bxt_ddi_pll_get_freq()
2466 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2481 a->pll2 == b->pll2 && in bxt_compare_hw_state()
/drivers/clk/qcom/
A Dmmcc-msm8960.c43 static struct clk_pll pll2 = { variable
102 { .hw = &pll2.clkr.hw },
115 { .hw = &pll2.clkr.hw },
129 { .hw = &pll2.clkr.hw },
2848 [PLL2] = &pll2.clkr,
3026 [PLL2] = &pll2.clkr,

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