Searched refs:pll9 (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_dpll_mgr.h | 208 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| A D | intel_dpll_mgr.c | 2102 PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9); in bxt_ddi_pll_enable()
2213 hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2214 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2350 hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5); in bxt_ddi_set_dpll_hw_state()
2467 hw_state->pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10, in bxt_dump_hw_state()
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