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Searched refs:pll_base (Results 1 – 19 of 19) sorted by relevance

/drivers/clk/imx/
A Dclk-imxrt1050.c39 void __iomem *pll_base; in imxrt1050_clocks_probe() local
56 pll_base = devm_of_iomap(dev, anp, 0, NULL); in imxrt1050_clocks_probe()
58 if (WARN_ON(IS_ERR(pll_base))) { in imxrt1050_clocks_probe()
59 ret = PTR_ERR(pll_base); in imxrt1050_clocks_probe()
67 pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imxrt1050_clocks_probe()
76 "pll1_arm_ref_sel", pll_base + 0x0, 0x7f); in imxrt1050_clocks_probe()
78 "pll2_sys_ref_sel", pll_base + 0x30, 0x1); in imxrt1050_clocks_probe()
80 "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1); in imxrt1050_clocks_probe()
82 "pll5_video_ref_sel", pll_base + 0xa0, 0x7f); in imxrt1050_clocks_probe()
95 "pll5_video", pll_base + 0xa0, 19, 2); in imxrt1050_clocks_probe()
[all …]
A Dclk-imx5.c283 void __iomem *pll_base; in mx50_clocks_init() local
287 WARN_ON(!pll_base); in mx50_clocks_init()
291 WARN_ON(!pll_base); in mx50_clocks_init()
295 WARN_ON(!pll_base); in mx50_clocks_init()
372 WARN_ON(!pll_base); in mx51_clocks_init()
376 WARN_ON(!pll_base); in mx51_clocks_init()
380 WARN_ON(!pll_base); in mx51_clocks_init()
478 WARN_ON(!pll_base); in mx53_clocks_init()
482 WARN_ON(!pll_base); in mx53_clocks_init()
486 WARN_ON(!pll_base); in mx53_clocks_init()
[all …]
/drivers/clk/visconti/
A Dpll.c21 void __iomem *pll_base; member
161 reg = readl(pll->pll_base + PLL_CTRL_REG); in visconti_pll_is_enabled()
180 reg = readl(pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
182 writel(reg, pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
186 reg = readl(pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
188 writel(reg, pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
192 reg = readl(pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
194 writel(reg, pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
198 reg = readl(pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
200 writel(reg, pll->pll_base + PLL_CTRL_REG); in visconti_pll_enable()
[all …]
/drivers/clk/microchip/
A Dclk-mpfs-ccc.c37 void __iomem **pll_base; member
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] + in mpfs_ccc_register_outputs()
209 pll_hw->base = data->pll_base[i]; in mpfs_ccc_register_plls()
233 void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)]; in mpfs_ccc_probe() local
245 pll_base[0] = devm_platform_ioremap_resource(pdev, 0); in mpfs_ccc_probe()
246 if (IS_ERR(pll_base[0])) in mpfs_ccc_probe()
247 return PTR_ERR(pll_base[0]); in mpfs_ccc_probe()
249 pll_base[1] = devm_platform_ioremap_resource(pdev, 1); in mpfs_ccc_probe()
250 if (IS_ERR(pll_base[1])) in mpfs_ccc_probe()
251 return PTR_ERR(pll_base[1]); in mpfs_ccc_probe()
[all …]
/drivers/gpu/drm/omapdrm/dss/
A Dvideo-pll.c141 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
148 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]); in dss_video_pll_init()
149 if (IS_ERR(pll_base)) in dss_video_pll_init()
150 return ERR_CAST(pll_base); in dss_video_pll_init()
179 pll->base = pll_base; in dss_video_pll_init()
A Ddsi.h343 void __iomem *pll_base; member
A Ddsi.c94 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
108 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
4543 pll->base = dsi->pll_base; in dsi_init_pll_data()
4933 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll"); in dsi_probe()
4934 if (IS_ERR(dsi->pll_base)) in dsi_probe()
4935 return PTR_ERR(dsi->pll_base); in dsi_probe()
/drivers/video/fbdev/omap2/omapfb/dss/
A Dvideo-pll.c133 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
140 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]); in dss_video_pll_init()
141 if (IS_ERR(pll_base)) { in dss_video_pll_init()
143 return ERR_CAST(pll_base); in dss_video_pll_init()
175 pll->base = pll_base; in dss_video_pll_init()
A Ddsi.c295 void __iomem *pll_base; member
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
457 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
5225 pll->base = dsi->pll_base; in dsi_init_pll_data()
5350 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, in dsi_bind()
5352 if (!dsi->pll_base) { in dsi_bind()
/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_28nm_8960.c78 val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()
98 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
142 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
176 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare()
229 writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); in dsi_pll_28nm_vco_unprepare()
343 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_save_state()
359 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_restore_state()
411 bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; in pll_28nm_register()
432 &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base + in pll_28nm_register()
A Ddsi_phy_28nm.c102 void __iomem *base = pll_28nm->phy->pll_base; in pll_28nm_software_reset()
122 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
246 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
293 void __iomem *base = pll_28nm->phy->pll_base; in _dsi_pll_28nm_vco_prepare_hpm()
397 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare_8226()
471 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare_lp()
584 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_save_state()
601 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_restore_state()
652 pll_28nm->phy->pll_base + in pll_28nm_register()
666 &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base + in pll_28nm_register()
[all …]
A Ddsi_phy_10nm.c186 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit()
210 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg()
234 void __iomem *base = pll->phy->pll_base; in dsi_pll_commit()
288 rc = readl_poll_timeout_atomic(pll->phy->pll_base + in dsi_pll_10nm_lock_status()
305 writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_disable_pll_bias()
315 writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_enable_pll_bias()
412 void __iomem *base = pll_10nm->phy->pll_base; in dsi_pll_10nm_vco_recalc_rate()
479 cached->pll_out_div = readl(pll_10nm->phy->pll_base + in dsi_10nm_pll_save_state()
503 val = readl(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_10nm_pll_restore_state()
506 writel(val, pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_10nm_pll_restore_state()
[all …]
A Ddsi_phy_7nm.c230 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit()
254 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg()
318 void __iomem *base = pll->phy->pll_base; in dsi_pll_commit()
373 rc = readl_poll_timeout_atomic(pll->phy->pll_base + in dsi_pll_7nm_lock_status()
390 writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_disable_pll_bias()
400 writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_enable_pll_bias()
529 void __iomem *base = pll_7nm->phy->pll_base; in dsi_pll_7nm_vco_recalc_rate()
596 cached->pll_out_div = readl(pll_7nm->phy->pll_base + in dsi_7nm_pll_save_state()
619 val = readl(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_7nm_pll_restore_state()
622 writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_7nm_pll_restore_state()
[all …]
A Ddsi_phy_14nm.c115 void __iomem *base = pll_14nm->phy->pll_base; in pll_14nm_poll_for_ready()
287 void __iomem *base = pll->phy->pll_base; in pll_db_commit_ssc()
322 void __iomem *base = pll->phy->pll_base; in pll_db_commit_common()
389 void __iomem *base = pll->phy->pll_base; in pll_db_commit_14nm()
498 void __iomem *base = pll_14nm->phy->pll_base; in dsi_pll_14nm_vco_recalc_rate()
537 void __iomem *base = pll_14nm->phy->pll_base; in dsi_pll_14nm_vco_prepare()
746 void __iomem *base = phy->pll_base; in dsi_14nm_set_usecase()
A Ddsi_phy.h98 void __iomem *pll_base; member
A Ddsi_phy.c670 phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size); in dsi_phy_driver_probe()
671 if (IS_ERR(phy->pll_base)) in dsi_phy_driver_probe()
672 return dev_err_probe(dev, PTR_ERR(phy->pll_base), in dsi_phy_driver_probe()
877 phy->pll_size, phy->pll_base, in msm_dsi_phy_snapshot()
/drivers/clk/
A Dclk-sp7021.c588 #define PLLA_CTL (pll_base + 0x1c)
589 #define PLLE_CTL (pll_base + 0x30)
590 #define PLLF_CTL (pll_base + 0x34)
591 #define PLLTV_CTL (pll_base + 0x38)
601 void __iomem *clk_base, *pll_base, *sys_base; in sp7021_clk_probe() local
609 pll_base = devm_platform_ioremap_resource(pdev, 1); in sp7021_clk_probe()
610 if (IS_ERR(pll_base)) in sp7021_clk_probe()
611 return PTR_ERR(pll_base); in sp7021_clk_probe()
A Dclk-bm1880.c63 void __iomem *pll_base; member
530 void __iomem *pll_base = data->pll_base; in bm1880_clk_register_plls() local
536 hw = bm1880_clk_register_pll(bm1880_clk, pll_base); in bm1880_clk_register_plls()
877 void __iomem *pll_base, *sys_base; in bm1880_clk_probe() local
881 pll_base = devm_platform_ioremap_resource(pdev, 0); in bm1880_clk_probe()
882 if (IS_ERR(pll_base)) in bm1880_clk_probe()
883 return PTR_ERR(pll_base); in bm1880_clk_probe()
900 clk_data->pll_base = pll_base; in bm1880_clk_probe()
/drivers/clk/st/
A Dclkgen-pll.c755 void __iomem *pll_base; in clkgen_c32_pll_setup() local
765 pll_base = clkgen_get_register_base(np); in clkgen_c32_pll_setup()
766 if (!pll_base) in clkgen_c32_pll_setup()
771 clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags, in clkgen_c32_pll_setup()
808 clk = clkgen_odf_register(pll_name, pll_base, datac->data, in clkgen_c32_pll_setup()

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