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Searched refs:pll_div (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/x86/
A Dclk-lgm.c196 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
198 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
200 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
205 pll_div),
207 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
211 1, 0, 0, pll_div),
214 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
218 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
221 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
231 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
[all …]
/drivers/clk/imx/
A Dclk-fracn-gppll.c162 u32 pll_numerator, pll_denominator, pll_div; in clk_fracn_gppll_recalc_rate() local
174 pll_div = readl_relaxed(pll->base + PLL_DIV); in clk_fracn_gppll_recalc_rate()
175 mfi = FIELD_GET(PLL_MFI_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
177 rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
178 odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
236 u32 tmp, pll_div, ana_mfn; in clk_fracn_gppll_set_rate() local
259 pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | in clk_fracn_gppll_set_rate()
261 writel_relaxed(pll_div, pll->base + PLL_DIV); in clk_fracn_gppll_set_rate()
A Dclk-pll14xx.c275 u32 pll_div) in clk_pll14xx_mp_change() argument
279 old_mdiv = FIELD_GET(MDIV_MASK, pll_div); in clk_pll14xx_mp_change()
280 old_pdiv = FIELD_GET(PDIV_MASK, pll_div); in clk_pll14xx_mp_change()
/drivers/gpu/drm/i915/display/
A Dvlv_dsi_pll.c125 u32 pll_ctl, pll_div; in vlv_dsi_pclk() local
131 pll_div = config->dsi_pll.div; in vlv_dsi_pclk()
138 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; in vlv_dsi_pclk()
142 pll_div &= DSI_PLL_M1_DIV_MASK; in vlv_dsi_pclk()
143 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; in vlv_dsi_pclk()
157 if (lfsr_converts[i] == pll_div) in vlv_dsi_pclk()
326 u32 pll_ctl, pll_div; in vlv_dsi_get_pclk() local
332 pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER); in vlv_dsi_get_pclk()
336 config->dsi_pll.div = pll_div; in vlv_dsi_get_pclk()
/drivers/clk/meson/
A Dvid-pll-div.c79 struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk); in meson_vid_pll_div_recalc_rate() local
82 div = _get_table_val(meson_parm_read(clk->map, &pll_div->val), in meson_vid_pll_div_recalc_rate()
83 meson_parm_read(clk->map, &pll_div->sel)); in meson_vid_pll_div_recalc_rate()
/drivers/clk/
A Dclk-stm32f4.c814 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL); in clk_register_pll_div()
815 if (!pll_div) in clk_register_pll_div()
825 pll_div->div.reg = reg; in clk_register_pll_div()
826 pll_div->div.shift = shift; in clk_register_pll_div()
827 pll_div->div.width = width; in clk_register_pll_div()
829 pll_div->div.lock = lock; in clk_register_pll_div()
830 pll_div->div.table = table; in clk_register_pll_div()
831 pll_div->div.hw.init = &init; in clk_register_pll_div()
833 pll_div->hw_pll = pll_hw; in clk_register_pll_div()
836 hw = &pll_div->div.hw; in clk_register_pll_div()
[all …]
/drivers/net/wireless/ath/ath9k/
A Dar9002_phy.c308 int pll_div = 0x2c; in ar9002_hw_compute_pll_control() local
314 pll_div = 0x50; in ar9002_hw_compute_pll_control()
316 pll_div = 0x28; in ar9002_hw_compute_pll_control()
321 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
/drivers/clk/qcom/
A Dgcc-ipq4019.c87 static u64 clk_fepll_vco_calc_rate(struct clk_fepll *pll_div, in clk_fepll_vco_calc_rate() argument
90 const struct clk_fepll_vco *pll_vco = pll_div->pll_vco; in clk_fepll_vco_calc_rate()
94 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); in clk_fepll_vco_calc_rate()
/drivers/media/i2c/
A Dds90ub960.c2306 u8 pll_div; in ub960_init_tx_ports_ub9702() local
2312 pll_div = 0x10; in ub960_init_tx_ports_ub9702()
2317 pll_div = 0x10; in ub960_init_tx_ports_ub9702()
2322 pll_div = 0x18; in ub960_init_tx_ports_ub9702()
2327 pll_div = 0x0f; in ub960_init_tx_ports_ub9702()
2333 pll_div = 0x10; in ub960_init_tx_ports_ub9702()
2338 pll_div = 0x19; in ub960_init_tx_ports_ub9702()
2344 ub960_write(priv, UB9702_SR_CSI_PLL_DIV, pll_div, &ret); in ub960_init_tx_ports_ub9702()

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