Home
last modified time | relevance | path

Searched refs:pll_settings (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.c197 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance() argument
253 struct pll_settings *pll_settings, in calc_pll_dividers_in_range() argument
295 struct pll_settings *pll_settings) in calculate_pixel_clock_pll_dividers() argument
399 struct pll_settings *pll_settings) in pll_adjust_pix_clk() argument
477 struct pll_settings *pll_settings, in dce110_get_pix_clk_dividers_helper() argument
539 struct pll_settings *pll_settings, in dce112_get_pix_clk_dividers_helper() argument
571 struct pll_settings *pll_settings) in dce110_get_pix_clk_dividers() argument
604 struct pll_settings *pll_settings) in dce112_get_pix_clk_dividers() argument
848 struct pll_settings *pll_settings) in dce110_program_pix_clk() argument
922 struct pll_settings *pll_settings) in dce112_program_pix_clk() argument
[all …]
/drivers/gpu/drm/amd/display/dc/inc/
A Dclock_source.h107 struct pll_settings { struct
168 struct pll_settings *);
172 struct pll_settings *);
A Dcore_types.h453 struct pll_settings pll_settings; member
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c495 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1462 pipe_ctx->pll_settings.feedback_divider; in build_audio_output()
1472 pipe_ctx->pll_settings.ss_percentage; in build_audio_output()
1547 &pipe_ctx->pll_settings)) { in dce110_enable_stream_timing()
3305 &pipes[i].pll_settings); in dce110_enable_dp_link_output()
/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c108 &pipes[i]->pll_settings); in dp_retrain_link_dp_test()
/drivers/gpu/drm/amd/display/dc/resource/dce110/
A Ddce110_resource.c923 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
/drivers/gpu/drm/amd/display/dc/resource/dcn10/
A Ddcn10_resource.c1037 &pipe_ctx->pll_settings); in build_pipe_hw_param()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c805 &pipe_ctx->pll_settings)) { in dcn401_enable_stream_timing()
1020 &pipe_ctx->pll_settings); in disable_link_output_symclk_on_tx_off()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c552 &otg_master->pll_settings); in dcn401_update_clocks_update_dtb_dto()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1384 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c1732 &pipe_ctx->pll_settings); in dcn401_build_pipe_pix_clk_params()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1288 &pipe_ctx->pll_settings); in dcn20_build_pipe_pix_clk_params()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c882 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1170 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()

Completed in 63 milliseconds