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Searched refs:pllclk (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/starfive/
A Dclk-starfive-jh7110-sys.c408 struct clk *pllclk; in jh7110_syscrg_probe() local
424 pllclk = clk_get(priv->dev, "pll0_out"); in jh7110_syscrg_probe()
425 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
433 ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); in jh7110_syscrg_probe()
439 pllclk = clk_get(priv->dev, "pll1_out"); in jh7110_syscrg_probe()
440 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
447 clk_put(pllclk); in jh7110_syscrg_probe()
451 pllclk = clk_get(priv->dev, "pll2_out"); in jh7110_syscrg_probe()
452 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
459 clk_put(pllclk); in jh7110_syscrg_probe()
/drivers/clk/
A Dclk-xgene.c61 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local
64 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
74 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local
82 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
84 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
85 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
114 pllclk->version); in xgene_clk_pll_recalc_rate()

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