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Searched refs:pmisc_addr (Results 1 – 11 of 11) sorted by relevance

/drivers/crypto/intel/qat/qat_common/
A Dadf_gen4_pfvf.c42 val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask; in adf_gen4_enable_vf2pf_interrupts()
43 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val); in adf_gen4_enable_vf2pf_interrupts()
48 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_all_vf2pf_interrupts()
56 sources = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU); in adf_gen4_disable_pending_vf2pf_interrupts()
61 disabled = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
75 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
86 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen4_pfvf_send() local
96 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT); in adf_gen4_pfvf_send()
102 true, pmisc_addr, pfvf_offset); in adf_gen4_pfvf_send()
113 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen4_pfvf_recv() local
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A Dadf_gen2_hw_data.c31 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen2_enable_error_correction() local
40 ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i), val); in adf_gen2_enable_error_correction()
48 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_UERRSSMSH(i)); in adf_gen2_enable_error_correction()
50 ADF_CSR_WR(pmisc_addr, ADF_GEN2_UERRSSMSH(i), val); in adf_gen2_enable_error_correction()
51 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_CERRSSMSH(i)); in adf_gen2_enable_error_correction()
53 ADF_CSR_WR(pmisc_addr, ADF_GEN2_CERRSSMSH(i), val); in adf_gen2_enable_error_correction()
67 reg = READ_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i); in adf_gen2_cfg_iov_thds()
72 WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i, reg); in adf_gen2_cfg_iov_thds()
77 reg = READ_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i); in adf_gen2_cfg_iov_thds()
82 WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i, reg); in adf_gen2_cfg_iov_thds()
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A Dadf_gen2_pfvf.c58 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_enable_vf2pf_interrupts()
60 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_enable_vf2pf_interrupts()
67 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_disable_all_vf2pf_interrupts()
69 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_disable_all_vf2pf_interrupts()
101 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
106 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
216 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send()
230 true, pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send()
255 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_send()
287 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_recv()
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A Dadf_isr.c61 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_enable_vf2pf_interrupts() local
65 GET_PFVF_OPS(accel_dev)->enable_vf2pf_interrupts(pmisc_addr, vf_mask); in adf_enable_vf2pf_interrupts()
71 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_disable_all_vf2pf_interrupts() local
75 GET_PFVF_OPS(accel_dev)->disable_all_vf2pf_interrupts(pmisc_addr); in adf_disable_all_vf2pf_interrupts()
81 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_disable_pending_vf2pf_interrupts() local
85 pending = GET_PFVF_OPS(accel_dev)->disable_pending_vf2pf_interrupts(pmisc_addr); in adf_disable_pending_vf2pf_interrupts()
A Dadf_vf_isr.c34 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_enable_pf2vf_interrupts() local
36 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x0); in adf_enable_pf2vf_interrupts()
41 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_disable_pf2vf_interrupts() local
43 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x2); in adf_disable_pf2vf_interrupts()
A Dadf_rl.c267 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in assign_rps_to_leaf() local
275 ADF_CSR_WR(pmisc_addr, offset, node_id); in assign_rps_to_leaf()
283 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in assign_leaf_to_cluster() local
290 ADF_CSR_WR(pmisc_addr, offset, parent_id); in assign_leaf_to_cluster()
297 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in assign_cluster_to_root() local
304 ADF_CSR_WR(pmisc_addr, offset, parent_id); in assign_cluster_to_root()
1087 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_rl_start() local
1102 ADF_CSR_WR(pmisc_addr, rl_hw_data->pciin_tb_offset, in adf_rl_start()
1104 ADF_CSR_WR(pmisc_addr, rl_hw_data->pciout_tb_offset, in adf_rl_start()
A Dadf_admin.c543 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_init_admin_comms() local
577 mailbox = pmisc_addr + mailbox_offset; in adf_init_admin_comms()
582 ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val)); in adf_init_admin_comms()
583 ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val)); in adf_init_admin_comms()
A Dqat_hal.c687 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in qat_hal_chip_init() local
726 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET_4XXX; in qat_hal_chip_init()
727 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET_4XXX; in qat_hal_chip_init()
728 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET_4XXX; in qat_hal_chip_init()
754 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET; in qat_hal_chip_init()
755 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET; in qat_hal_chip_init()
756 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET; in qat_hal_chip_init()
781 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET; in qat_hal_chip_init()
782 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET; in qat_hal_chip_init()
783 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET; in qat_hal_chip_init()
A Dadf_gen4_hw_data.c145 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen4_set_ssm_wdtimer() local
150 ADF_CSR_WR64_LO_HI(pmisc_addr, ADF_SSMWDTL_OFFSET, ADF_SSMWDTH_OFFSET, timer_val); in adf_gen4_set_ssm_wdtimer()
153 ADF_CSR_WR64_LO_HI(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ADF_SSMWDTPKEH_OFFSET, in adf_gen4_set_ssm_wdtimer()
A Dadf_accel_devices.h233 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
234 void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr);
235 u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
/drivers/crypto/intel/qat/qat_dh895xcc/
A Dadf_dh895xcc_hw_data.c127 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in enable_vf2pf_interrupts()
129 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in enable_vf2pf_interrupts()
134 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in enable_vf2pf_interrupts()
136 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in enable_vf2pf_interrupts()
145 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in disable_all_vf2pf_interrupts()
147 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in disable_all_vf2pf_interrupts()
150 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in disable_all_vf2pf_interrupts()
152 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in disable_all_vf2pf_interrupts()
191 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in disable_pending_vf2pf_interrupts()
192 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5); in disable_pending_vf2pf_interrupts()
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