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Searched refs:port_base (Results 1 – 21 of 21) sorted by relevance

/drivers/net/ethernet/silan/
A Dsc92031.c356 void __iomem *port_base = priv->port_base; in sc92031_disable_interrupts() local
374 void __iomem *port_base = priv->port_base; in sc92031_enable_interrupts() local
387 void __iomem *port_base = priv->port_base; in _sc92031_disable_tx_rx() local
398 void __iomem *port_base = priv->port_base; in _sc92031_enable_tx_rx() local
420 void __iomem *port_base = priv->port_base; in _sc92031_set_mar() local
458 void __iomem *port_base = priv->port_base; in _sc92031_set_rx_config() local
488 void __iomem *port_base = priv->port_base; in _sc92031_check_media() local
553 void __iomem *port_base = priv->port_base; in _sc92031_phy_reset() local
597 void __iomem *port_base = priv->port_base; in _sc92031_reset() local
650 void __iomem *port_base = priv->port_base; in _sc92031_tx_tasklet() local
[all …]
/drivers/scsi/pcmcia/
A Dsym53c500_cs.c356 int port_base = dev->io_port; in SYM53C500_intr() local
367 REG1(port_base); in SYM53C500_intr()
369 REG0(port_base); in SYM53C500_intr()
432 REG0(port_base); in SYM53C500_intr()
451 REG0(port_base); in SYM53C500_intr()
571 REG0(port_base); in SYM53C500_queue_lck()
703 int irq_level, port_base; in SYM53C500_config() local
753 chip_init(port_base); in SYM53C500_config()
777 host->unique_id = port_base; in SYM53C500_config()
779 host->io_port = port_base; in SYM53C500_config()
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/drivers/ata/
A Dsata_inic162x.c288 writeb(0xff, port_base + PORT_IRQ_STAT); in inic_reset_port()
321 readb(port_base + PORT_RPQ_FIFO); in inic_stop_idma()
322 readb(port_base + PORT_RPQ_CNT); in inic_stop_idma()
323 writew(0, port_base + PORT_IDMA_CTL); in inic_stop_idma()
551 writeb(0, port_base + PORT_CPB_PTQFIFO); in inic_qc_issue()
594 writeb(0xff, port_base + PORT_IRQ_STAT); in inic_freeze()
601 writeb(0xff, port_base + PORT_IRQ_STAT); in inic_thaw()
626 inic_reset_port(port_base); in inic_hardreset()
666 inic_reset_port(port_base); in inic_error_handler()
779 writeb(0xff, port_base + PORT_IRQ_MASK); in init_controller()
[all …]
A Dpdc_adma.c585 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no); in adma_ata_init_one() local
586 unsigned int offset = port_base - mmio_base; in adma_ata_init_one()
588 adma_ata_setup_port(&ap->ioaddr, port_base); in adma_ata_init_one()
A Dsata_mv.c1258 void __iomem *port_base; in mv_dump_all_regs() local
1282 port_base = mv_port_base(mmio_base, p); in mv_dump_all_regs()
1284 mv_dump_mem(&pdev->dev, port_base, 0x54); in mv_dump_all_regs()
1286 mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); in mv_dump_all_regs()
/drivers/net/ethernet/ti/
A Dam65-cpsw-qos.c47 writel(0, port->port_base + AM65_CPSW_PN_REG_PRI_CIR(prio)); in am65_cpsw_tx_pn_shaper_reset()
48 writel(0, port->port_base + AM65_CPSW_PN_REG_PRI_EIR(prio)); in am65_cpsw_tx_pn_shaper_reset()
87 port->port_base + AM65_CPSW_PN_REG_PRI_CIR(prio)); in am65_cpsw_tx_pn_shaper_apply()
99 port->port_base + AM65_CPSW_PN_REG_PRI_EIR(prio)); in am65_cpsw_tx_pn_shaper_apply()
198 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); in am65_cpsw_reset_tc_mqprio()
361 val = readl(port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_iet_common_enable()
391 val = readl(port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_iet_commit_preemptible_tcs()
460 val = readl(port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_port_est_enable()
466 writel(val, port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_port_est_enable()
476 val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL); in am65_cpsw_port_est_assign_buf_num()
[all …]
A Dam65-cpsw-ethtool.c759 val = readl(port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_port_iet_rx_enable()
765 writel(val, port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_port_iet_rx_enable()
773 val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL); in am65_cpsw_port_iet_tx_enable()
779 writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL); in am65_cpsw_port_iet_tx_enable()
794 iet_ctrl = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL); in am65_cpsw_get_mm()
795 port_ctrl = readl(port->port_base + AM65_CPSW_PN_REG_CTL); in am65_cpsw_get_mm()
800 iet_status = readl(port->port_base + AM65_CPSW_PN_REG_IET_STATUS); in am65_cpsw_get_mm()
859 port->port_base + AM65_CPSW_PN_REG_MAX_BLKS); in am65_cpsw_set_mm()
863 port->port_base + AM65_CPSW_PN_REG_MAX_BLKS); in am65_cpsw_set_mm()
869 val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL); in am65_cpsw_set_mm()
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A Dam65-cpsw-nuss.c183 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); in am65_cpsw_port_set_sl_mac()
184 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); in am65_cpsw_port_set_sl_mac()
274 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); in am65_cpsw_port_enable_dscp_map()
277 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); in am65_cpsw_port_enable_dscp_map()
285 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); in am65_cpsw_sl_ctl_reset()
480 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); in am65_cpsw_nuss_set_p0_ptype()
495 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); in am65_cpsw_nuss_set_p0_ptype()
884 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); in am65_cpsw_nuss_common_open()
889 host_p->port_base + AM65_CPSW_P0_REG_CTL); in am65_cpsw_nuss_common_open()
1866 writel(ts_vlan_ltype, port->port_base + in am65_cpsw_nuss_hwtstamp_set()
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A Dam65-cpsw-switchdev.c124 pvid = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); in am65_cpsw_get_pvid()
126 pvid = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); in am65_cpsw_get_pvid()
144 writel(pvid, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); in am65_cpsw_set_pvid()
146 writel(pvid, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); in am65_cpsw_set_pvid()
A Dam65-cpsw-nuss.h48 void __iomem *port_base; member
72 void __iomem *port_base; member
/drivers/phy/mediatek/
A Dphy-mtk-xsphy.c95 void __iomem *port_base; member
124 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
182 void __iomem *pbase = inst->port_base; in u2_phy_instance_init()
193 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_on()
208 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_off()
226 tmp = readl(inst->port_base + XSP_U2PHYDTM1); in u2_phy_instance_set_mode()
241 writel(tmp, inst->port_base + XSP_U2PHYDTM1); in u2_phy_instance_set_mode()
287 void __iomem *pbase = inst->port_base; in u2_phy_props_set()
309 void __iomem *pbase = inst->port_base; in u3_phy_props_set()
577 if (IS_ERR(inst->port_base)) { in mtk_xsphy_probe()
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A Dphy-mtk-tphy.c314 void __iomem *port_base; member
1087 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; in phy_v1_banks_init()
1088 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; in phy_v1_banks_init()
1091 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; in phy_v1_banks_init()
1107 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; in phy_v2_banks_init()
1113 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; in phy_v2_banks_init()
1114 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; in phy_v2_banks_init()
1115 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; in phy_v2_banks_init()
1641 instance->port_base = devm_ioremap_resource(subdev, &res); in mtk_tphy_probe()
1642 if (IS_ERR(instance->port_base)) in mtk_tphy_probe()
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/drivers/media/pci/intel/ipu6/
A Dipu6-isys-jsl-phy.c176 u32 port_base; in ipu6_isys_csi2_set_timing() local
179 port_base = (port % 2) ? CSI2_SIP_TOP_CSI_RX_PORT_BASE_1(port) : in ipu6_isys_csi2_set_timing()
184 reg = isys->pdata->base + port_base; in ipu6_isys_csi2_set_timing()
189 reg = isys->pdata->base + port_base; in ipu6_isys_csi2_set_timing()
194 reg = isys->pdata->base + port_base; in ipu6_isys_csi2_set_timing()
198 reg = isys->pdata->base + port_base; in ipu6_isys_csi2_set_timing()
/drivers/net/ethernet/hisilicon/
A Dhisi_femac.c109 void __iomem *port_base; member
204 writel(status, priv->port_base + MAC_PORTSET); in hisi_femac_adjust_link()
239 writel(addr, priv->port_base + IQ_ADDR); in hisi_femac_rx_refill()
507 val = readl(priv->port_base + ADDRQ_STAT); in hisi_femac_net_xmit()
538 writel(addr, priv->port_base + EQ_ADDR); in hisi_femac_net_xmit()
740 writel(val, priv->port_base + MAC_PORTSEL); in hisi_femac_port_init()
755 val = readl(priv->port_base + MAC_SET); in hisi_femac_port_init()
758 writel(val, priv->port_base + MAC_SET); in hisi_femac_port_init()
765 writel(val, priv->port_base + QLEN_SET); in hisi_femac_port_init()
789 if (IS_ERR(priv->port_base)) { in hisi_femac_drv_probe()
[all …]
/drivers/phy/ralink/
A Dphy-mt7621-pci.c81 void __iomem *port_base; member
276 mt7621_phy->port_base, mt7621_phy->has_dual_port); in mt7621_pcie_phy_of_xlate()
311 phy->port_base = devm_platform_ioremap_resource(pdev, 0); in mt7621_pci_phy_probe()
312 if (IS_ERR(phy->port_base)) { in mt7621_pci_phy_probe()
314 return PTR_ERR(phy->port_base); in mt7621_pci_phy_probe()
317 phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base, in mt7621_pci_phy_probe()
/drivers/pinctrl/sunxi/
A Dpinctrl-sunxi-dt.c79 int port_base = desc->pin_base / PINS_PER_BANK; in init_pins_table() local
121 port_base + 'A' + i, j); in init_pins_table()
123 cur_pin->pin.number = (port_base + i) * PINS_PER_BANK + j; in init_pins_table()
/drivers/net/dsa/
A Ddsa_loop.c143 ret = mdiobus_read_nested(bus, ps->port_base + port, regnum); in dsa_loop_phy_read()
159 ret = mdiobus_write_nested(bus, ps->port_base + port, regnum, value); in dsa_loop_phy_write()
217 mdiobus_read(bus, ps->port_base + port, MII_BMSR); in dsa_loop_port_vlan_add()
246 mdiobus_read(bus, ps->port_base + port, MII_BMSR); in dsa_loop_port_vlan_del()
/drivers/net/phy/
A Dmicrochip_rds_ptp.h215 u16 clk_base, u16 port_base);
227 u16 port_base) in mchp_rds_ptp_probe() argument
/drivers/net/wireless/realtek/rtw89/
A Dmac.c4209 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_check_packet_ctrl()
4232 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_bcn_drop()
4270 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_func_sw()
4320 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_tx_rpt()
4334 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_rx_rpt()
4348 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_net_type()
4358 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_bcn_prct()
4372 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_rx_sw()
4387 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_rx_sync()
4408 const struct rtw89_port_reg *p = mac->port_base; in rtw89_mac_port_cfg_tx_sw()
[all …]
A Dmac.h986 const struct rtw89_port_reg *port_base; member
A Dmac_be.c2572 .port_base = &rtw89_port_base_be,

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