| /drivers/gpu/drm/i915/display/ |
| A D | intel_ddi_buf_trans.c | 1306 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1335 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1360 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1385 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1412 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1463 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1476 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1507 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1550 if (crtc_state->port_clock > 270000) in adls_get_combo_buf_trans_dp()
1561 if (crtc_state->port_clock > 540000) in adls_get_combo_buf_trans_edp()
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| A D | intel_cx0_phy.c | 431 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
2061 bool is_dp, int port_clock, in intel_c10pll_calc_state_from_table() argument
2092 crtc_state->port_clock, in intel_c10pll_calc_state()
2100 crtc_state->port_clock); in intel_c10pll_calc_state()
2253 if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000) in intel_c20_compute_hdmi_tmds_pll()
2626 bool is_dp, int port_clock) in intel_c20_pll_program() argument
2756 bool is_dp, int port_clock, in intel_program_port_clock_ctl() argument
2778 if (port_clock == 1000000 || port_clock == 2000000) in intel_program_port_clock_ctl()
3219 crtc_state->port_clock); in intel_mtl_tbt_pll_enable()
3632 int port_clock = 162000; in intel_cx0_pll_power_save_wa() local
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| A D | intel_dpll.c | 431 int port_clock; in i9xx_crtc_clock_get() local
512 crtc_state->port_clock = port_clock; in i9xx_crtc_clock_get()
983 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1402 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1494 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1521 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1568 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1608 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1646 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1688 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
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| A D | intel_pmdemand.c | 172 enum pipe pipe, int port_clock) in intel_pmdemand_update_port_clock() argument
177 pmdemand_state->ddi_clocks[pipe] = port_clock; in intel_pmdemand_update_port_clock()
193 new_crtc_state->port_clock); in intel_pmdemand_update_max_ddiclk()
312 if (new_crtc_state->port_clock != old_crtc_state->port_clock) in intel_pmdemand_needs_update()
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| A D | intel_alpm.c | 134 static int _lnl_compute_aux_less_wake_time(int port_clock) in _lnl_compute_aux_less_wake_time() argument
142 int tml_phy_lock = 1000 * 1000 * tps4 / port_clock; in _lnl_compute_aux_less_wake_time()
160 _lnl_compute_aux_less_wake_time(crtc_state->port_clock); in _lnl_compute_aux_less_alpm_params()
164 if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock, in _lnl_compute_aux_less_alpm_params()
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| A D | intel_ddi.c | 267 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
304 switch (port_clock) { in ddi_buf_phy_link_rate()
322 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
346 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); in dp_phy_lane_stagger_delay()
1155 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
2631 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
2750 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2903 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
3884 if (crtc_state->port_clock > 594000) in tgl_ddi_min_voltage_level()
3892 if (crtc_state->port_clock > 594000) in jsl_ddi_min_voltage_level()
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| A D | intel_dp_link_training.c | 730 crtc_state->port_clock, crtc_state->vrr.in_range); in intel_dp_update_downspread_ctrl()
782 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
979 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
997 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
1171 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1201 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); in reduce_link_params_in_bw_order()
1266 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); in reduce_link_params_in_rate_lane_order()
1318 crtc_state->lane_count, crtc_state->port_clock, in intel_dp_get_link_train_fallback_values()
1590 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_128b132b_link_train()
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| A D | g4x_dp.c | 84 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
103 pipe_config->port_clock, in intel_dp_prepare()
206 pipe_config->port_clock); in ilk_edp_pll_on()
210 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
396 pipe_config->port_clock = 162000; in intel_dp_get_config()
398 pipe_config->port_clock = 270000; in intel_dp_get_config()
402 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
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| A D | intel_pmdemand.h | 28 enum pipe pipe, int port_clock);
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| A D | intel_audio.c | 248 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
469 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
507 link_clk = crtc_state->port_clock; in calc_samples_room()
784 crtc_state->port_clock, in intel_audio_codec_enable()
1010 crtc_state->port_clock >= 540000 && in intel_audio_min_cdclk()
1037 min_cdclk = max(min_cdclk, crtc_state->port_clock); in intel_audio_min_cdclk()
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| A D | intel_dpll_mgr.c | 1079 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1099 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1817 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, in skl_ddi_hdmi_pll_dividers()
1859 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2282 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2291 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
2299 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2404 crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2707 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2790 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
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| A D | intel_dp_mst.c | 172 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
216 crtc_state->port_clock, in intel_dp_mst_compute_m_n()
290 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, in intel_dp_mtp_tu_compute_config()
447 crtc_state->port_clock = limits->max_rate; in mst_stream_compute_link_config()
511 crtc_state->port_clock = limits->max_rate; in mst_stream_dsc_compute_link_config()
1178 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()
1184 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
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| A D | intel_dpio_phy.c | 983 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
985 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
987 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
989 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
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| A D | vlv_dsi_pll.c | 205 config->port_clock = pclk; in vlv_dsi_pll_compute()
526 config->port_clock = pclk; in bxt_dsi_pll_compute()
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| A D | intel_dp.c | 147 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
1612 if (display->platform.g4x && port_clock == 268800) in intel_dp_compute_rate()
1613 port_clock = 270000; in intel_dp_compute_rate()
1619 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1802 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1998 pipe_config->port_clock = link_rate; in dsc_compute_link_config()
2323 pipe_config->port_clock = limits->max_rate; in intel_edp_dsc_compute_pipe_bpp()
2706 pipe_config->port_clock, in intel_dp_compute_link_config()
3006 pipe_config->port_clock, in intel_dp_drrs_compute_config()
3284 pipe_config->port_clock, in intel_dp_compute_config()
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| A D | intel_tv.c | 1126 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1153 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1219 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1227 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); in intel_tv_compute_config()
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| A D | g4x_hdmi.c | 194 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); in intel_hdmi_get_config()
196 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
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| A D | intel_dp.h | 112 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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| A D | intel_crt.c | 154 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_crt_get_config()
467 crtc_state->port_clock = 135000 * 2; in hsw_crt_compute_config()
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| A D | intel_modeset_setup.c | 570 crtc_state->port_clock == 0; in has_bogus_dpll_config()
867 crtc_state->port_clock); in intel_modeset_readout_hw_state()
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| A D | intel_crtc_state_dump.c | 317 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), in intel_crtc_state_dump()
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| A D | intel_dvo.c | 182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
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| A D | intel_display.c | 3111 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
4058 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
4061 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
4064 dotclock = pipe_config->port_clock; in intel_crtc_dotclock()
4689 crtc_state->port_clock = 0; in intel_modeset_pipe_config()
4720 if (!crtc_state->port_clock) in intel_modeset_pipe_config()
4721 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
5359 PIPE_CONF_CHECK_I(port_clock); in intel_pipe_config_compare()
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| A D | intel_lvds.c | 153 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
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| A D | intel_snps_phy.c | 1802 if (crtc_state->port_clock == tables[i]->clock) { in intel_mpllb_calc_state()
1811 crtc_state->port_clock); in intel_mpllb_calc_state()
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