| /drivers/clk/mediatek/ |
| A D | clk-pll.c | 41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
64 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
94 int postdiv) in mtk_pll_set_rate_regs() argument
158 *postdiv = 1 << val; in mtk_pll_calc_values()
161 *postdiv = 1 << val; in mtk_pll_calc_values()
162 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
180 u32 postdiv; in mtk_pll_set_rate() local
183 mtk_pll_set_rate_regs(pll, pcw, postdiv); in mtk_pll_set_rate()
191 u32 postdiv; in mtk_pll_recalc_rate() local
195 postdiv = 1 << postdiv; in mtk_pll_recalc_rate()
[all …]
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| A D | clk-fhctl.c | 171 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) in __set_postdiv() argument
177 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift; in __set_postdiv()
182 unsigned int postdiv) in fhctl_hopping() argument
193 if (postdiv) { in fhctl_hopping()
196 if (postdiv > pll_postdiv) in fhctl_hopping()
197 __set_postdiv(pll, postdiv); in fhctl_hopping()
206 if (postdiv && postdiv < pll_postdiv) in fhctl_hopping()
207 __set_postdiv(pll, postdiv); in fhctl_hopping()
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| A D | clk-pllfh.c | 33 u32 postdiv; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
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| A D | clk-pllfh.h | 67 unsigned int postdiv);
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| A D | clk-pll.h | 95 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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| /drivers/clk/mmp/ |
| A D | clk-audio.c | 121 unsigned int postdiv; in audio_pll_recalc_rate() local
140 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
146 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
159 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
171 unsigned int postdiv; in audio_pll_round_rate() local
177 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_round_rate()
180 freq /= postdivs[postdiv].divisor; in audio_pll_round_rate()
199 unsigned int postdiv; in audio_pll_set_rate() local
206 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_set_rate()
207 if (rate * postdivs[postdiv].divisor != predivs[prediv].freq_vco) in audio_pll_set_rate()
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| A D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
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| /drivers/clk/keystone/ |
| A D | pll.c | 60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
172 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
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| /drivers/media/i2c/ |
| A D | tc358746.c | 926 u8 postdiv; in tc358746_find_pll_settings() local
934 postdiv = 1; in tc358746_find_pll_settings()
936 postdiv = 2; in tc358746_find_pll_settings()
938 postdiv = 4; in tc358746_find_pll_settings()
940 postdiv = 8; in tc358746_find_pll_settings()
950 tmp = fout * postdiv; in tc358746_find_pll_settings()
956 do_div(tmp, postdiv); in tc358746_find_pll_settings()
1155 if (postdiv % 2) in tc358746_find_mclk_settings()
1158 if (postdiv >= 4 && postdiv <= 512) { in tc358746_find_mclk_settings()
1160 mclk_postdiv = postdiv; in tc358746_find_mclk_settings()
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| A D | ov2659.c | 897 u32 prediv, postdiv, mult; in ov2659_pll_calc_params() local
903 postdiv = ctrl1[i].div; in ov2659_pll_calc_params()
910 actual /= postdiv; in ov2659_pll_calc_params()
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| /drivers/gpu/drm/msm/dsi/phy/ |
| A D | dsi_phy_14nm.c | 610 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
612 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
613 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
622 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
630 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
635 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
636 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
643 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_set_rate()
646 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_set_rate()
647 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_set_rate()
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| /drivers/gpu/drm/bridge/ |
| A D | lontium-lt9611.c | 174 … lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) in lt9611_pcr_setup() argument
176 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; in lt9611_pcr_setup()
224 …lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) in lt9611_pll_setup() argument
245 *postdiv = 1; in lt9611_pll_setup()
248 *postdiv = 2; in lt9611_pll_setup()
251 *postdiv = 4; in lt9611_pll_setup()
652 unsigned int postdiv; in lt9611_bridge_atomic_enable() local
669 lt9611_pll_setup(lt9611, mode, &postdiv); in lt9611_bridge_atomic_enable()
671 lt9611_pcr_setup(lt9611, mode, postdiv); in lt9611_bridge_atomic_enable()
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| /drivers/clk/ |
| A D | clk-tps68470.c | 35 unsigned int postdiv; member
171 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
172 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
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| A D | clk-axm5516.c | 52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
56 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
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| /drivers/clk/visconti/ |
| A D | pll.c | 59 u32 postdiv, val; in visconti_pll_get_params() local
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
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| /drivers/clk/imx/ |
| A D | clk-composite-8m.c | 52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
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| /drivers/video/fbdev/ |
| A D | gxt4500.c | 239 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
249 postdiv = pdiv1 * pdiv2; in calc_pll()
250 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
258 n = intf * postdiv / period_ps; in calc_pll()
261 t = par->refclk_ps * m * postdiv / n; in calc_pll()
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| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | vegam_smumgr.c | 683 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
702 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
704 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
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| A D | polaris10_smumgr.c | 860 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; in polaris10_get_sclk_range_table()
874 …le[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
875 …le[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
878 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
930 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
931 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
938 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
945 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
946 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
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| /drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-hdmi.c | 270 u8 postdiv; member
1076 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
1080 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
1182 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1188 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
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| /drivers/net/can/rcar/ |
| A D | rcar_canfd.c | 457 u8 postdiv; member
630 .postdiv = 2,
647 .postdiv = 2,
664 .postdiv = 1,
681 .postdiv = 1,
2052 fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv; in rcar_canfd_probe()
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| /drivers/clk/rockchip/ |
| A D | clk-pll.c | 902 u64 rate64 = prate, postdiv; in rockchip_rk3588_pll_recalc_rate() local
913 postdiv = cur.p * 65535; in rockchip_rk3588_pll_recalc_rate()
914 do_div(frac_rate64, postdiv); in rockchip_rk3588_pll_recalc_rate()
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| /drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | smu74_discrete.h | 45 uint8_t postdiv; member
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| A D | smu75_discrete.h | 44 uint8_t postdiv; /* divide by 2^n */ member
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| /drivers/gpu/drm/radeon/ |
| A D | rv770_dpm.c | 344 static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) in rv770_encode_yclk_post_div() argument
348 switch (postdiv) { in rv770_encode_yclk_post_div()
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