| /drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| A D | dcn302_hwseq.c | 58 DOMAIN1_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
66 DOMAIN3_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
74 DOMAIN5_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
82 DOMAIN7_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
90 DOMAIN9_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
115 DOMAIN0_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
123 DOMAIN2_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
131 DOMAIN4_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
139 DOMAIN6_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
147 DOMAIN8_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
[all …]
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| /drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| A D | dcn35_pg_cntl.c | 79 uint32_t power_gate = power_on ? 0 : 1; in pg_cntl35_dsc_pg_control() local
110 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
118 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
126 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
134 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
188 uint32_t power_gate = power_on ? 0 : 1; in pg_cntl35_hubp_dpp_pg_control() local
215 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
220 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
261 uint32_t power_gate = power_on ? 0 : 1; in pg_cntl35_hpo_pg_control() local
309 uint32_t power_gate = power_on ? 0 : 1; in pg_cntl35_io_clk_pg_control() local
[all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| A D | dcn31_hwseq.c | 286 uint32_t power_gate = power_on ? 0 : 1; in dcn31_dsc_pg_control() local
306 DOMAIN_POWER_GATE, power_gate); in dcn31_dsc_pg_control()
314 DOMAIN_POWER_GATE, power_gate); in dcn31_dsc_pg_control()
322 DOMAIN_POWER_GATE, power_gate); in dcn31_dsc_pg_control()
450 uint32_t power_gate = power_on ? 0 : 1; in dcn31_hubp_pg_control() local
464 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
468 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
472 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
476 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
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| /drivers/gpu/drm/amd/pm/swsmu/ |
| A D | amdgpu_smu.c | 254 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_vcn_enable() local
280 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_jpeg_enable() local
294 atomic_set(&power_gate->jpeg_gated, !enable); in smu_dpm_set_jpeg_enable()
303 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_vpe_enable() local
309 if (atomic_read(&power_gate->vpe_gated) ^ enable) in smu_dpm_set_vpe_enable()
314 atomic_set(&power_gate->vpe_gated, !enable); in smu_dpm_set_vpe_enable()
323 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_isp_enable() local
329 if (atomic_read(&power_gate->isp_gated) ^ enable) in smu_dpm_set_isp_enable()
334 atomic_set(&power_gate->isp_gated, !enable); in smu_dpm_set_isp_enable()
343 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_umsch_mm_enable() local
[all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| A D | dcn314_hwseq.c | 229 uint32_t power_gate = power_on ? 0 : 1; in dcn314_dsc_pg_control() local
249 DOMAIN_POWER_GATE, power_gate); in dcn314_dsc_pg_control()
257 DOMAIN_POWER_GATE, power_gate); in dcn314_dsc_pg_control()
265 DOMAIN_POWER_GATE, power_gate); in dcn314_dsc_pg_control()
273 DOMAIN_POWER_GATE, power_gate); in dcn314_dsc_pg_control()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 74 uint32_t power_gate = power_on ? 0 : 1; in dcn32_dsc_pg_control() local
89 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst); in dcn32_dsc_pg_control()
93 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
101 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
109 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
117 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
165 uint32_t power_gate = power_on ? 0 : 1; in dcn32_hubp_pg_control() local
176 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
180 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
184 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
[all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 496 DOMAIN16_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
567 DOMAIN1_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
575 DOMAIN3_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
583 DOMAIN5_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
591 DOMAIN7_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
599 DOMAIN9_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
641 DOMAIN0_POWER_GATE, power_gate); in dcn20_hubp_pg_control()
649 DOMAIN2_POWER_GATE, power_gate); in dcn20_hubp_pg_control()
657 DOMAIN4_POWER_GATE, power_gate); in dcn20_hubp_pg_control()
665 DOMAIN6_POWER_GATE, power_gate); in dcn20_hubp_pg_control()
[all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 508 uint32_t power_gate = power_on ? 0 : 1; in dcn35_dsc_pg_control() local
523 DOMAIN_POWER_GATE, power_gate); in dcn35_dsc_pg_control()
531 DOMAIN_POWER_GATE, power_gate); in dcn35_dsc_pg_control()
539 DOMAIN_POWER_GATE, power_gate); in dcn35_dsc_pg_control()
547 DOMAIN_POWER_GATE, power_gate); in dcn35_dsc_pg_control()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 864 uint32_t power_gate = power_on ? 0 : 1; in dcn10_dpp_pg_control() local
875 DOMAIN1_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
883 DOMAIN3_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
891 DOMAIN5_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
899 DOMAIN7_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
925 uint32_t power_gate = power_on ? 0 : 1; in dcn10_hubp_pg_control() local
936 DOMAIN0_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
944 DOMAIN2_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
952 DOMAIN4_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
960 DOMAIN6_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
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| /drivers/gpu/drm/amd/pm/swsmu/inc/ |
| A D | amdgpu_smu.h | 412 struct smu_power_gate power_gate; member
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| /drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 2572 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ member
|