Searched refs:pp_feature (Results 1 – 22 of 22) sorted by relevance
99 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in hwmgr_early_init()110 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in hwmgr_early_init()117 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in hwmgr_early_init()159 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in hwmgr_early_init()169 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
352 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { in smu10_disable_gfx_off()372 if (adev->pm.pp_feature & PP_GFXOFF_MASK) in smu10_enable_gfx_off()
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { in sienna_cichlid_get_allowed_feature_mask()315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && in sienna_cichlid_get_allowed_feature_mask()320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) in sienna_cichlid_get_allowed_feature_mask()325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) in sienna_cichlid_get_allowed_feature_mask()328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) in sienna_cichlid_get_allowed_feature_mask()331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) in sienna_cichlid_get_allowed_feature_mask()334 if (adev->pm.pp_feature & PP_ULV_MASK) in sienna_cichlid_get_allowed_feature_mask()337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in sienna_cichlid_get_allowed_feature_mask()340 if (adev->pm.pp_feature & PP_GFXOFF_MASK) in sienna_cichlid_get_allowed_feature_mask()2163 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in sienna_cichlid_update_pcie_parameters()[all …]
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) in navi10_get_allowed_feature_mask()313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) in navi10_get_allowed_feature_mask()316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) in navi10_get_allowed_feature_mask()319 if (adev->pm.pp_feature & PP_ULV_MASK) in navi10_get_allowed_feature_mask()322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in navi10_get_allowed_feature_mask()325 if (adev->pm.pp_feature & PP_GFXOFF_MASK) in navi10_get_allowed_feature_mask()343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) in navi10_get_allowed_feature_mask()350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) in navi10_get_allowed_feature_mask()451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { in navi10_append_powerplay_table()
2229 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in vangogh_post_smu_init()2443 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in vangogh_set_gfxoff_residency()2491 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in vangogh_get_gfxoff_entrycount()
1117 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in smu_v11_0_gfx_off_control()
280 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { in smu_v13_0_7_get_allowed_feature_mask()286 if (adev->pm.pp_feature & PP_GFXOFF_MASK) in smu_v13_0_7_get_allowed_feature_mask()289 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { in smu_v13_0_7_get_allowed_feature_mask()298 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) in smu_v13_0_7_get_allowed_feature_mask()301 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in smu_v13_0_7_get_allowed_feature_mask()304 if (adev->pm.pp_feature & PP_ULV_MASK) in smu_v13_0_7_get_allowed_feature_mask()327 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) in smu_v13_0_7_get_allowed_feature_mask()2758 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in smu_v13_0_7_update_pcie_parameters()
309 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { in smu_v13_0_0_get_allowed_feature_mask()318 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) in smu_v13_0_0_get_allowed_feature_mask()323 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) in smu_v13_0_0_get_allowed_feature_mask()326 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { in smu_v13_0_0_get_allowed_feature_mask()332 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) in smu_v13_0_0_get_allowed_feature_mask()335 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in smu_v13_0_0_get_allowed_feature_mask()340 if (!(adev->pm.pp_feature & PP_ULV_MASK)) in smu_v13_0_0_get_allowed_feature_mask()3170 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in smu_v13_0_0_update_pcie_parameters()3315 smu->adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in smu_v13_0_0_set_ppt_funcs()
796 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in smu_v13_0_gfx_off_control()2395 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in smu_v13_0_update_pcie_parameters()
279 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { in smu_v14_0_2_get_allowed_feature_mask()288 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) in smu_v14_0_2_get_allowed_feature_mask()294 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) in smu_v14_0_2_get_allowed_feature_mask()297 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { in smu_v14_0_2_get_allowed_feature_mask()303 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) in smu_v14_0_2_get_allowed_feature_mask()306 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in smu_v14_0_2_get_allowed_feature_mask()311 if (!(adev->pm.pp_feature & PP_ULV_MASK)) in smu_v14_0_2_get_allowed_feature_mask()1495 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { in smu_v14_0_2_update_pcie_parameters()
779 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in smu_v14_0_gfx_off_control()
234 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in smu10_start_smu()
366 uint32_t pp_feature; member
1511 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in amdgpu_acpi_is_s0ix_active()
2776 adev->pm.pp_feature = amdgpu_pp_feature_mask; in amdgpu_device_ip_early_init()2778 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in amdgpu_device_ip_early_init()2780 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; in amdgpu_device_ip_early_init()2782 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK; in amdgpu_device_ip_early_init()
1421 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in gfx_v9_0_check_if_need_gfxoff()1436 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in gfx_v9_0_check_if_need_gfxoff()1438 if (adev->pm.pp_feature & PP_GFXOFF_MASK) in gfx_v9_0_check_if_need_gfxoff()1444 if (adev->pm.pp_feature & PP_GFXOFF_MASK) in gfx_v9_0_check_if_need_gfxoff()
782 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in amdgpu_gfx_do_off_ctrl()
4198 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in gfx_v10_0_check_gfxoff_flag()
62 hwmgr->feature_mask = adev->pm.pp_feature; in amd_powerplay_create()
712 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) in smu_set_funcs()751 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; in smu_set_funcs()
2816 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in kv_dpm_init()
4452 } else if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) { in amdgpu_pm_sysfs_init()
Completed in 139 milliseconds