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Searched refs:pp_smu_wm_range_sets (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h89 struct pp_smu_wm_range_sets { struct
114 struct pp_smu_wm_range_sets *ranges); argument
219 struct pp_smu_wm_range_sets *ranges);
283 struct pp_smu_wm_range_sets *ranges);
302 struct pp_smu_wm_range_sets *ranges);
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.h33 struct pp_smu_wm_range_sets *ranges,
A Ddcn301_fpu.c389 struct pp_smu_wm_range_sets *ranges, in dcn301_fpu_set_wm_ranges()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.h67 struct pp_smu_wm_range_sets *ranges,
A Ddcn20_fpu.c2132 struct pp_smu_wm_range_sets *ranges, in dcn20_fpu_set_wm_ranges()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c465 struct pp_smu_wm_range_sets *ranges) in pp_rv_set_wm_ranges()
554 struct pp_smu_wm_range_sets *ranges) in pp_nv_set_wm_ranges()
743 struct pp_smu_wm_range_sets *ranges) in pp_rn_set_wm_ranges()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h357 struct pp_smu_wm_range_sets ranges;
/drivers/gpu/drm/amd/include/
A Dkgd_pp_interface.h359 struct pp_smu_wm_range_sets;
502 struct pp_smu_wm_range_sets *ranges);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c454 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ra… in build_watermark_ranges()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h836 struct pp_smu_wm_range_sets *clock_ranges);
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_5_ppt.c409 struct pp_smu_wm_range_sets *clock_ranges) in smu_v13_0_5_set_watermarks_table()
A Dsmu_v13_0_4_ppt.c664 struct pp_smu_wm_range_sets *clock_ranges) in smu_v13_0_4_set_watermarks_table()
A Dyellow_carp_ppt.c500 struct pp_smu_wm_range_sets *clock_ranges) in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c1061 struct pp_smu_wm_range_sets *clock_ranges) in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c1326 struct pp_smu_wm_range_sets ranges = {0}; in set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c483 struct pp_smu_wm_range_sets *clock_ranges) in smu_v14_0_0_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c1374 struct pp_smu_wm_range_sets ranges = {0}; in dcn_bw_notify_pplib_of_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c1591 struct pp_smu_wm_range_sets *clock_ranges) in vangogh_set_watermarks_table()
A Dsienna_cichlid_ppt.c1874 struct pp_smu_wm_range_sets *clock_ranges) in sienna_cichlid_set_watermarks_table()
A Dnavi10_ppt.c2172 struct pp_smu_wm_range_sets *clock_ranges) in navi10_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c2568 struct pp_smu_wm_range_sets ranges = {0}; in dcn20_resource_construct()
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c2687 struct pp_smu_wm_range_sets *clock_ranges) in smu_set_watermarks_for_clock_ranges()

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