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Searched refs:ppc (Results 1 – 22 of 22) sorted by relevance

/drivers/staging/media/atomisp/pci/css_2401_system/hrt/
A Dmipi_backend_defs.h157 …IPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(s… argument
158 …MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(s… argument
166 …BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_wid… argument
197 …T_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid… argument
198 …RT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid… argument
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dctxgf117.c254 int gpc, ppc; in gf117_grctx_generate_attrib() local
260 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) { in gf117_grctx_generate_attrib()
261 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
262 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
264 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
266 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
270 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
272 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
286 .ppc = gf117_grctx_pack_ppc,
A Dctxgp102.c51 int gpc, ppc, n = 0; in gp102_grctx_generate_attrib() local
58 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { in gp102_grctx_generate_attrib()
59 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
63 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
64 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
66 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
76 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
A Dctxgm107.c909 int gpc, ppc, n = 0; in gm107_grctx_generate_attrib() local
915 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { in gm107_grctx_generate_attrib()
916 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
917 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
919 const u32 o = PPC_UNIT(gpc, ppc, 0); in gm107_grctx_generate_attrib()
921 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gm107_grctx_generate_attrib()
926 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
929 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
967 .ppc = gm107_grctx_pack_ppc,
A Dctxgp100.c52 int gpc, ppc, n = 0; in gp100_grctx_generate_attrib() local
59 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { in gp100_grctx_generate_attrib()
60 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
63 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
65 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
74 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
A Dctxgm200.c87 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
90 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) { in gm200_grctx_generate_dist_skip_table()
91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
95 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
A Dctxgv100.c73 int gpc, ppc, n = 0; in gv100_grctx_generate_attrib() local
80 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) { in gv100_grctx_generate_attrib()
81 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
85 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
87 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
96 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
A Dctxgk104.c925 int i, j, gpc, ppc; in gk104_grctx_generate_alpha_beta_tables() local
934 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) { in gk104_grctx_generate_alpha_beta_tables()
935 u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
946 pmask = gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
951 pmask ^= gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
977 .ppc = gk104_grctx_pack_ppc,
A Dgk104.c418 int gpc, ppc; in gk104_gr_init_ppc_exceptions() local
421 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) { in gk104_gr_init_ppc_exceptions()
422 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gk104_gr_init_ppc_exceptions()
424 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); in gk104_gr_init_ppc_exceptions()
A Dctxgk110b.c81 .ppc = gk110_grctx_pack_ppc,
A Dctxgk208.c547 .ppc = gk208_grctx_pack_ppc,
A Dctxgk110.c841 .ppc = gk110_grctx_pack_ppc,
A Dctxgf100.h20 const struct gf100_gr_pack *ppc; member
A Dctxgf100.c1357 gf100_gr_mmio(gr, grctx->ppc); in gf100_grctx_generate_main()
A Dgf100.c1865 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); in gf100_gr_init_ctxctl_int()
/drivers/acpi/
A Dprocessor_perflib.c54 unsigned long long ppc = 0; in acpi_processor_get_platform_limit() local
66 status = acpi_evaluate_integer(pr->handle, "_PPC", NULL, &ppc); in acpi_processor_get_platform_limit()
76 index = ppc; in acpi_processor_get_platform_limit()
79 ppc >= pr->performance->state_count) in acpi_processor_get_platform_limit()
/drivers/gpu/drm/vc4/
A Dvc4_crtc.c364 u8 ppc = pv_data->pixels_per_clock; in vc4_crtc_config_pv() local
386 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
388 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
392 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
394 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
399 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc); in vc4_crtc_config_pv()
/drivers/gpu/drm/etnaviv/
A Detnaviv_gpu.c635 u32 pmc, ppc; in etnaviv_gpu_enable_mlcg() local
638 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
639 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; in etnaviv_gpu_enable_mlcg()
644 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; in etnaviv_gpu_enable_mlcg()
646 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
/drivers/video/fbdev/
A Dffb.c220 u32 ppc; member
436 &fbc->ppc); in ffb_switch_from_graph()
/drivers/gpu/drm/i915/display/
A Dintel_cdclk.c2798 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); in intel_pixel_rate_to_cdclk() local
2802 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); in intel_pixel_rate_to_cdclk()
3403 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); in intel_compute_max_dotclk() local
3407 return ppc * max_cdclk_freq * guardband / 100; in intel_compute_max_dotclk()
A Dintel_dp.c906 int ppc = 2; in bigjoiner_bw_max_bpp() local
909 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / in bigjoiner_bw_max_bpp()
/drivers/scsi/
A Dscsi_debug.c3346 int ppc, sp, pcode, subpcode; in resp_log_sense() local
3352 ppc = cmd[1] & 0x2; in resp_log_sense()
3354 if (ppc || sp) { in resp_log_sense()
3355 mk_sense_invalid_fld(scp, SDEB_IN_CDB, 1, ppc ? 1 : 0); in resp_log_sense()

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