Home
last modified time | relevance | path

Searched refs:pps (Results 1 – 25 of 146) sorted by relevance

123456

/drivers/pps/
A Dpps.c44 if (pps->last_fetched_ev == pps->last_ev) in pps_cdev_poll()
195 pps->last_fetched_ev = pps->last_ev; in pps_cdev_ioctl()
283 pps->last_fetched_ev = pps->last_ev; in pps_cdev_compat_ioctl()
312 if (pps) in pps_idr_get()
316 return pps; in pps_idr_get()
323 if (!pps) in pps_cdev_open()
358 kfree(pps); in pps_device_destruct()
382 pps->dev.parent = pps->info.dev; in pps_register_cdev()
383 pps->dev.devt = MKDEV(pps_major, pps->id); in pps_register_cdev()
384 dev_set_drvdata(&pps->dev, pps); in pps_register_cdev()
[all …]
A Dkapi.c68 struct pps_device *pps; in pps_register_source() local
87 if (pps == NULL) { in pps_register_source()
97 pps->info = *info; in pps_register_source()
117 return pps; in pps_register_source()
120 kfree(pps); in pps_register_source()
138 pps_kc_remove(pps); in pps_unregister_source()
178 pps->info.echo(pps, event, data); in pps_event()
181 pps->current_mode = pps->params.mode; in pps_event()
204 pps->clear_sequence++; in pps_event()
206 pps->clear_sequence); in pps_event()
[all …]
A Dsysfs.c21 struct pps_device *pps = dev_get_drvdata(dev); in assert_show() local
23 if (!(pps->info.mode & PPS_CAPTUREASSERT)) in assert_show()
27 (long long) pps->assert_tu.sec, pps->assert_tu.nsec, in assert_show()
28 pps->assert_sequence); in assert_show()
35 struct pps_device *pps = dev_get_drvdata(dev); in clear_show() local
37 if (!(pps->info.mode & PPS_CAPTURECLEAR)) in clear_show()
41 (long long) pps->clear_tu.sec, pps->clear_tu.nsec, in clear_show()
42 pps->clear_sequence); in clear_show()
51 return sprintf(buf, "%4x\n", pps->info.mode); in mode_show()
69 return sprintf(buf, "%s\n", pps->info.name); in name_show()
[all …]
A Dkc.c42 if (pps_kc_hardpps_dev == pps) { in pps_kc_bind()
46 dev_info(&pps->dev, "unbound kernel" in pps_kc_bind()
50 dev_err(&pps->dev, "selected kernel consumer" in pps_kc_bind()
56 pps_kc_hardpps_dev == pps) { in pps_kc_bind()
58 pps_kc_hardpps_dev = pps; in pps_kc_bind()
60 dev_info(&pps->dev, "bound kernel consumer: " in pps_kc_bind()
64 dev_err(&pps->dev, "another kernel consumer" in pps_kc_bind()
79 void pps_kc_remove(struct pps_device *pps) in pps_kc_remove() argument
82 if (pps == pps_kc_hardpps_dev) { in pps_kc_remove()
86 dev_info(&pps->dev, "unbound kernel consumer" in pps_kc_remove()
[all …]
A Dkc.h16 extern int pps_kc_bind(struct pps_device *pps,
18 extern void pps_kc_remove(struct pps_device *pps);
19 extern void pps_kc_event(struct pps_device *pps,
25 static inline int pps_kc_bind(struct pps_device *pps, in pps_kc_bind() argument
27 static inline void pps_kc_remove(struct pps_device *pps) {} in pps_kc_remove() argument
28 static inline void pps_kc_event(struct pps_device *pps, in pps_kc_event() argument
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c193 dsc_log_pps(dsc, &dsc20->reg_vals.pps); in dsc2_set_config()
213 dsc_log_pps(dsc, &dsc_reg_vals.pps); in dsc2_get_packed_pps()
284 int bits_per_pixel = pps->bits_per_pixel; in dsc_log_pps()
431 calc_rc_params(&rc, &dsc_reg_vals->pps); in dsc_prepare_config()
568 reg_vals->pps = dsc_params->pps; in dsc_update_from_dsc_parameters()
572 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; in dsc_update_from_dsc_parameters()
594 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
595 PIC_HEIGHT, reg_vals->pps.pic_height); in dsc_write_to_registers()
643 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
644 PIC_HEIGHT, reg_vals->pps.pic_height); in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c134 dsc_log_pps(dsc, &dsc401->reg_vals.pps); in dsc401_set_config()
247 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, in dsc_write_to_registers()
262 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); in dsc_write_to_registers()
265 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
266 PIC_HEIGHT, reg_vals->pps.pic_height); in dsc_write_to_registers()
269 SLICE_WIDTH, reg_vals->pps.slice_width, in dsc_write_to_registers()
270 SLICE_HEIGHT, reg_vals->pps.slice_height); in dsc_write_to_registers()
285 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, in dsc_write_to_registers()
289 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, in dsc_write_to_registers()
294 FINAL_OFFSET, reg_vals->pps.final_offset); in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_pps.c35 struct intel_pps *pps = &intel_dp->pps; in pps_name() local
38 switch (pps->vlv_pps_pipe) { in pps_name()
50 MISSING_CASE(pps->vlv_pps_pipe); in pps_name()
54 switch (pps->pps_idx) { in pps_name()
60 MISSING_CASE(pps->pps_idx); in pps_name()
77 mutex_lock(&display->pps.mutex); in intel_pps_lock()
218 intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe); in vlv_power_sequencer_pipe()
417 intel_dp->pps.pps_idx = 0; in pps_initial_setup()
420 intel_dp->pps.pps_idx = -1; in pps_initial_setup()
885 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps); in edp_panel_vdd_work()
[all …]
A Dintel_lvds.c157 struct intel_lvds_pps *pps) in intel_lvds_pps_get_hw_state() argument
187 pps->delays.power_up == 0 && in intel_lvds_pps_get_hw_state()
189 pps->delays.power_down == 0 && in intel_lvds_pps_get_hw_state()
195 pps->delays.power_up = 40 * 10; in intel_lvds_pps_get_hw_state()
198 pps->delays.power_down = 35 * 10; in intel_lvds_pps_get_hw_state()
204 pps->delays.power_up, pps->delays.power_down, in intel_lvds_pps_get_hw_state()
205 pps->delays.power_cycle, pps->delays.backlight_on, in intel_lvds_pps_get_hw_state()
206 pps->delays.backlight_off, pps->divider, in intel_lvds_pps_get_hw_state()
207 pps->port, pps->powerdown_on_reset); in intel_lvds_pps_get_hw_state()
211 struct intel_lvds_pps *pps) in intel_lvds_pps_init_hw() argument
[all …]
A Dintel_vdsc_regs.h58 #define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) argument
59 #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) argument
81 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) argument
82 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) argument
83 #define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) argument
/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc.c40 void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) in calc_rc_params() argument
46 u16 drm_bpp = pps->bits_per_pixel; in calc_rc_params()
47 int slice_width = pps->slice_width; in calc_rc_params()
48 int slice_height = pps->slice_height; in calc_rc_params()
50 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : in calc_rc_params()
51 (pps->native_422 ? CM_422 : in calc_rc_params()
52 pps->native_420 ? CM_420 : CM_444)); in calc_rc_params()
53 bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) in calc_rc_params()
56 is_navite_422_or_420 = pps->native_422 || pps->native_420; in calc_rc_params()
61 pps->dsc_version_minor); in calc_rc_params()
A Drc_calc_dpi.c98 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, in dscc_compute_dsc_parameters() argument
105 dsc_params->pps = *pps; in dscc_compute_dsc_parameters()
106 …dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_ful… in dscc_compute_dsc_parameters()
108 copy_pps_fields(&dsc_cfg, &dsc_params->pps); in dscc_compute_dsc_parameters()
111 dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64; in dscc_compute_dsc_parameters()
118 copy_pps_fields(&dsc_params->pps, &dsc_cfg); in dscc_compute_dsc_parameters()
/drivers/media/platform/allegro-dvt/
A Dnal-hevc.c443 rbsp_sev(rbsp, &pps->init_qp_minus26); in nal_hevc_rbsp_pps()
447 if (pps->cu_qp_delta_enabled_flag) in nal_hevc_rbsp_pps()
457 if (pps->tiles_enabled_flag) { in nal_hevc_rbsp_pps()
461 if (!pps->uniform_spacing_flag) { in nal_hevc_rbsp_pps()
486 if (pps->pps_extension_present_flag) { in nal_hevc_rbsp_pps()
493 if (pps->pps_range_extension_flag) in nal_hevc_rbsp_pps()
497 if (pps->pps_3d_extension_flag) in nal_hevc_rbsp_pps()
499 if (pps->pps_scc_extension_flag) in nal_hevc_rbsp_pps()
501 if (pps->pps_extension_4bits) in nal_hevc_rbsp_pps()
731 nal_hevc_rbsp_pps(&rbsp, pps); in nal_hevc_write_pps()
[all …]
A Dnal-h264.c292 if (pps->num_slice_groups_minus1 > 0) { in nal_h264_rbsp_pps()
294 switch (pps->slice_group_map_type) { in nal_h264_rbsp_pps()
301 rbsp_uev(rbsp, &pps->top_left[i]); in nal_h264_rbsp_pps()
302 rbsp_uev(rbsp, &pps->bottom_right[i]); in nal_h264_rbsp_pps()
314 &pps->slice_group_id[i]); in nal_h264_rbsp_pps()
322 rbsp_bit(rbsp, &pps->weighted_pred_flag); in nal_h264_rbsp_pps()
324 rbsp_sev(rbsp, &pps->pic_init_qp_minus26); in nal_h264_rbsp_pps()
325 rbsp_sev(rbsp, &pps->pic_init_qs_minus26); in nal_h264_rbsp_pps()
333 if (pps->pic_scaling_matrix_present_flag) in nal_h264_rbsp_pps()
464 nal_h264_rbsp_pps(&rbsp, pps); in nal_h264_write_pps()
[all …]
/drivers/pps/clients/
A Dpps-ldisc.c18 struct pps_device *pps; in pps_tty_dcd_change() local
23 pps = pps_lookup_dev(tty); in pps_tty_dcd_change()
28 if (WARN_ON_ONCE(pps == NULL)) in pps_tty_dcd_change()
46 struct pps_device *pps; in pps_tty_open() local
59 if (IS_ERR(pps)) { in pps_tty_open()
61 return PTR_ERR(pps); in pps_tty_open()
63 pps->lookup_cookie = tty; in pps_tty_open()
77 pps_unregister_source(pps); in pps_tty_open()
89 if (WARN_ON(!pps)) in pps_tty_close()
92 dev_info(&pps->dev, "removed\n"); in pps_tty_close()
[all …]
A Dpps-ktimer.c21 static struct pps_device *pps; variable
35 pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL); in pps_ktimer_event()
59 dev_dbg(&pps->dev, "ktimer PPS source unregistered\n"); in pps_ktimer_exit()
62 pps_unregister_source(pps); in pps_ktimer_exit()
67 pps = pps_register_source(&pps_ktimer_info, in pps_ktimer_init()
69 if (IS_ERR(pps)) { in pps_ktimer_init()
71 return PTR_ERR(pps); in pps_ktimer_init()
77 dev_dbg(&pps->dev, "ktimer PPS source registered\n"); in pps_ktimer_init()
A Dpps-gpio.c29 struct pps_device *pps; /* PPS source device */ member
60 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
64 pps_event(info->pps, &ts, PPS_CAPTURECLEAR, data); in pps_gpio_irq_handler()
79 if (pps->params.mode & PPS_ECHOASSERT) in pps_gpio_echo()
84 if (pps->params.mode & PPS_ECHOCLEAR) in pps_gpio_echo()
90 if (info->pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) { in pps_gpio_echo()
206 if (IS_ERR(data->pps)) { in pps_gpio_probe()
209 return PTR_ERR(data->pps); in pps_gpio_probe()
216 pps_unregister_source(data->pps); in pps_gpio_probe()
221 dev_dbg(&data->pps->dev, "Registered IRQ %d as PPS source\n", in pps_gpio_probe()
[all …]
A Dpps_parport.c41 struct pps_device *pps; /* PPS device */ member
84 dev_err(&dev->pps->dev, "lost the signal\n"); in parport_irq()
101 dev_err(&dev->pps->dev, "disabled clear edge capture after %d" in parport_irq()
109 pps_event(dev->pps, &ts_assert, in parport_irq()
115 pps_event(dev->pps, &ts_assert, in parport_irq()
118 pps_event(dev->pps, &ts_clear, in parport_irq()
173 device->pps = pps_register_source(&info, in parport_attach()
175 if (IS_ERR(device->pps)) { in parport_attach()
212 pps_unregister_source(device->pps); in parport_detach()
/drivers/media/platform/verisilicon/
A Dhantro_g2_hevc_dec.c15 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps; in prepare_tile_info_buffer() local
57 h = pps->row_height_minus1[i] + 1; in prepare_tile_info_buffer()
62 tmp_w += pps->column_width_minus1[j] + 1; in prepare_tile_info_buffer()
63 *p++ = pps->column_width_minus1[j] + 1; in prepare_tile_info_buffer()
86 (pps->column_width_minus1[0] + 1) == 1 && in prepare_tile_info_buffer()
111 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps; in compute_header_skip_length() local
145 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps; in set_params() local
239 pps->log2_parallel_merge_level_minus2 + 2); in set_params()
280 pps->num_ref_idx_l0_default_active_minus1 + 1); in set_params()
282 pps->num_ref_idx_l1_default_active_minus1 + 1); in set_params()
[all …]
A Dhantro_g1_h264_dec.c27 const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; in set_params() local
58 reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | in set_params()
61 if (pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) in set_params()
69 G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | in set_params()
76 G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc); in set_params()
77 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) in set_params()
83 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) in set_params()
90 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) in set_params()
94 if (pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) in set_params()
96 if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) in set_params()
[all …]
A Drockchip_vpu2_hw_h264_dec.c198 const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; in set_params() local
209 reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) | in set_params()
261 reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) | in set_params()
262 VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) | in set_params()
267 reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) | in set_params()
281 reg = VDPU_REG_PPS_ID(pps->pic_parameter_set_id) | in set_params()
282 VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | in set_params()
283 VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | in set_params()
290 VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) | in set_params()
291 VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) | in set_params()
[all …]
/drivers/staging/media/sunxi/cedrus/
A Dcedrus_h265.c370 pps = run->h265.pps; in cedrus_h265_write_tiles()
440 pps = run->h265.pps; in cedrus_h265_setup()
622 pps->flags); in cedrus_h265_setup()
626 pps->flags); in cedrus_h265_setup()
630 pps->flags); in cedrus_h265_setup()
634 pps->flags); in cedrus_h265_setup()
642 pps->flags); in cedrus_h265_setup()
646 pps->flags); in cedrus_h265_setup()
650 pps->flags); in cedrus_h265_setup()
654 pps->flags); in cedrus_h265_setup()
[all …]
A Dcedrus_h264.c261 const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; in cedrus_write_scaling_lists() local
264 if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) in cedrus_write_scaling_lists()
346 const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; in cedrus_set_params() local
391 if (V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice)) in cedrus_set_params()
410 reg |= (pps->weighted_bipred_idc & 0x3) << 2; in cedrus_set_params()
411 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) in cedrus_set_params()
413 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) in cedrus_set_params()
415 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) in cedrus_set_params()
417 if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) in cedrus_set_params()
466 reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; in cedrus_set_params()
[all …]
/drivers/media/platform/rockchip/rkvdec/
A Drkvdec-h264.c110 const struct v4l2_ctrl_h264_pps *pps; member
638 const struct v4l2_ctrl_h264_pps *pps = run->pps; in assemble_hw_pps() local
653 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
698 WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1, in assemble_hw_pps()
700 WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1, in assemble_hw_pps()
704 WRITE_PPS(pps->weighted_bipred_idc, WEIGHTED_BIPRED_IDC); in assemble_hw_pps()
705 WRITE_PPS(pps->pic_init_qp_minus26, PIC_INIT_QP_MINUS26); in assemble_hw_pps()
706 WRITE_PPS(pps->pic_init_qs_minus26, PIC_INIT_QS_MINUS26); in assemble_hw_pps()
716 WRITE_PPS(pps->second_chroma_qp_index_offset, in assemble_hw_pps()
822 const struct v4l2_ctrl_h264_pps *pps = run->pps; in assemble_hw_scaling_list() local
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_vbif.c85 u64 pps; in _dpu_vbif_apply_dynamic_ot_limit() local
96 pps = params->frame_rate; in _dpu_vbif_apply_dynamic_ot_limit()
97 pps *= params->width; in _dpu_vbif_apply_dynamic_ot_limit()
98 pps *= params->height; in _dpu_vbif_apply_dynamic_ot_limit()
104 if (pps <= tbl->cfg[i].pps) { in _dpu_vbif_apply_dynamic_ot_limit()
113 pps, *ot_lim); in _dpu_vbif_apply_dynamic_ot_limit()
329 (u64 *)&cfg->pps); in dpu_debugfs_vbif_init()
343 (u64 *)&cfg->pps); in dpu_debugfs_vbif_init()

Completed in 764 milliseconds

123456