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Searched refs:pre_div (Results 1 – 25 of 26) sorted by relevance

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/drivers/clk/sunxi/
A Dclk-sun9i-cpus.c72 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
87 pre_div = div; in sun9i_a80_cpus_clk_round()
90 pre_div = DIV_ROUND_UP(div, 2); in sun9i_a80_cpus_clk_round()
93 pre_div = DIV_ROUND_UP(div, 3); in sun9i_a80_cpus_clk_round()
96 pre_div = DIV_ROUND_UP(div, 4); in sun9i_a80_cpus_clk_round()
104 *pre_divp = pre_div - 1; in sun9i_a80_cpus_clk_round()
107 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
154 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
163 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); in sun9i_a80_cpus_clk_set_rate()
166 reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); in sun9i_a80_cpus_clk_set_rate()
/drivers/gpu/drm/sun4i/
A Dsun4i_hdmi_ddc_clk.c18 u8 pre_div; member
29 const u8 pre_div, in sun4i_ddc_calc_divider() argument
40 tmp_rate = (((parent_rate / pre_div) / 10) >> _n) / in sun4i_ddc_calc_divider()
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
134 ddc->pre_div = hdmi->variant->ddc_clk_pre_divider; in sun4i_ddc_create()
/drivers/clk/qcom/
A Dclk-rcg2.c161 f->pre_div *= 2; in convert_to_reg_val()
162 f->pre_div -= 1; in convert_to_reg_val()
263 if (f->pre_div) { in _freq_tbl_determine_rate()
467 pre_div *= i; in clk_rcg2_calc_mnd()
478 f->pre_div = pre_div > 1 ? pre_div : 0; in clk_rcg2_calc_mnd()
660 f_tbl.pre_div = conf->pre_div; in __clk_rcg2_fm_set_rate()
1023 f.pre_div = div; in clk_byte_set_rate()
1082 f.pre_div = div; in clk_byte2_set_rate()
1612 f->pre_div = 1; in clk_rcg2_dfs_populate_freq()
1708 pre_div = 1; in clk_rcg2_dfs_recalc_rate()
[all …]
A Dclk-rcg.c120 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns) in pre_div_to_ns() argument
128 ns |= pre_div << p->pre_div_shift; in pre_div_to_ns()
203 struct pre_div *p; in configure_bank()
328 if (pre_div) in calc_rate()
329 rate /= pre_div + 1; in calc_rate()
349 pre_div = ns_to_pre_div(&rcg->p, ns); in clk_rcg_recalc_rate()
370 u32 m, n, pre_div, ns, md, mode, reg; in clk_dyn_rcg_recalc_rate() local
380 m = n = pre_div = mode = 0; in clk_dyn_rcg_recalc_rate()
418 rate = rate * f->pre_div; in _freq_tbl_determine_rate()
656 f.pre_div = 1; in clk_rcg_pixel_set_rate()
[all …]
A Dclk-rcg.h15 u8 pre_div; member
26 u8 pre_div; member
64 struct pre_div { struct
97 struct pre_div p;
136 struct pre_div p[2];
A Dgcc-ipq4019.c166 f->pre_div << pll->cdiv.shift); in clk_cpu_div_set_rate()
187 u32 cdiv, pre_div; in clk_cpu_div_recalc_rate() local
199 pre_div = (cdiv + 1) * 2; in clk_cpu_div_recalc_rate()
201 pre_div = cdiv + 12; in clk_cpu_div_recalc_rate()
204 do_div(rate, pre_div); in clk_cpu_div_recalc_rate()
264 u32 cdiv, pre_div = 1; in clk_regmap_clk_div_recalc_rate() local
269 pre_div = pll->fixed_div; in clk_regmap_clk_div_recalc_rate()
276 pre_div = clkt->div; in clk_regmap_clk_div_recalc_rate()
281 do_div(rate, pre_div); in clk_regmap_clk_div_recalc_rate()
A Dgpucc-msm8998.c132 { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
/drivers/clk/bcm/
A Dclk-kona-setup.c64 div = &peri->pre_div; in clk_requires_trigger()
130 div = &peri->pre_div; in peri_clk_data_offsets_valid()
364 struct bcm_clk_div *pre_div; in kona_dividers_valid() local
373 pre_div = &peri->pre_div; in kona_dividers_valid()
374 if (divider_is_fixed(div) || divider_is_fixed(pre_div)) in kona_dividers_valid()
379 return div->u.s.frac_width + pre_div->u.s.frac_width <= limit; in kona_dividers_valid()
400 struct bcm_clk_div *pre_div; in peri_clk_data_valid() local
442 pre_div = &peri->pre_div; in peri_clk_data_valid()
447 if (divider_exists(pre_div)) in peri_clk_data_valid()
448 if (!div_valid(pre_div, "pre-divider", name)) in peri_clk_data_valid()
[all …]
A Dclk-kona.c669 struct bcm_clk_div *div, struct bcm_clk_div *pre_div, in clk_recalc_rate() argument
691 if (pre_div && divider_exists(pre_div)) { in clk_recalc_rate()
694 scaled_rate = scale_rate(pre_div, parent_rate); in clk_recalc_rate()
696 scaled_div = divider_read_scaled(ccu, pre_div); in clk_recalc_rate()
724 struct bcm_clk_div *pre_div, in round_rate() argument
749 if (divider_exists(pre_div)) { in round_rate()
753 scaled_rate = scale_rate(pre_div, parent_rate); in round_rate()
755 scaled_pre_div = divider_read_scaled(ccu, pre_div); in round_rate()
993 return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div, in kona_peri_clk_round_rate()
1136 (void)round_rate(bcm_clk->ccu, div, &data->pre_div, in kona_peri_clk_set_rate()
[all …]
A Dclk-bcm281xx.c170 .pre_div = FIXED_DIVIDER(2),
A Dclk-kona.h387 struct bcm_clk_div pre_div; member
/drivers/phy/mediatek/
A Dphy-mtk-hdmi-mt8173.c140 unsigned int pre_div; in mtk_hdmi_pll_set_rate() local
150 pre_div = 0; in mtk_hdmi_pll_set_rate()
153 pre_div = 1; in mtk_hdmi_pll_set_rate()
156 pre_div = 1; in mtk_hdmi_pll_set_rate()
160 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); in mtk_hdmi_pll_set_rate()
/drivers/clk/
A Dclk-sparx5.c53 u8 pre_div; member
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
91 conf->pre_div = i; in s5_search_fractional()
183 val |= FIELD_PREP(PLL_PRE_DIV, conf.pre_div); in s5_pll_set_rate()
203 conf.pre_div = FIELD_GET(PLL_PRE_DIV, val); in s5_pll_recalc_rate()
/drivers/mmc/host/
A Dsdhci-of-esdhc.c653 unsigned int pre_div = 1, div = 1; in esdhc_of_set_clock() local
666 pre_div = 2; in esdhc_of_set_clock()
679 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256) in esdhc_of_set_clock()
680 pre_div *= 2; in esdhc_of_set_clock()
685 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
693 pre_div = 4; in esdhc_of_set_clock()
696 pre_div = 4; in esdhc_of_set_clock()
699 pre_div = 4; in esdhc_of_set_clock()
705 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
714 pre_div >>= 1; in esdhc_of_set_clock()
[all …]
A Dsdhci-esdhc-imx.c962 int pre_div = 1; in esdhc_pltfm_set_clock() local
990 pre_div = 2; in esdhc_pltfm_set_clock()
1007 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && in esdhc_pltfm_set_clock()
1008 pre_div < 256) in esdhc_pltfm_set_clock()
1009 pre_div *= 2; in esdhc_pltfm_set_clock()
1011 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) in esdhc_pltfm_set_clock()
1014 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
1018 pre_div >>= 1; in esdhc_pltfm_set_clock()
1024 | (pre_div << ESDHC_PREDIV_SHIFT)); in esdhc_pltfm_set_clock()
/drivers/rtc/
A Drtc-ac100.c226 int div = 0, pre_div = 0; in ac100_clkout_set_rate() local
229 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, in ac100_clkout_set_rate()
235 ac100_clkout_prediv[++pre_div].div); in ac100_clkout_set_rate()
240 pre_div = ac100_clkout_prediv[pre_div].val; in ac100_clkout_set_rate()
246 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT); in ac100_clkout_set_rate()
/drivers/media/i2c/
A Dov7251.c89 unsigned int pre_div; member
97 unsigned int pre_div; member
170 .pre_div = 0x03,
178 .pre_div = 0x01,
186 .pre_div = 0x03,
194 .pre_div = 0x05,
202 .pre_div = 0x04,
210 .pre_div = 0x04,
816 configs->pll1[ov7251->link_freq_idx]->pre_div); in ov7251_pll_configure()
840 configs->pll2->pre_div); in ov7251_pll_configure()
A Dccs-pll.c399 u32 pre_mul, pre_div; in ccs_pll_calculate_vt_tree() local
401 pre_div = gcd(pll->pixel_rate_csi, in ccs_pll_calculate_vt_tree()
403 pre_mul = pll->pixel_rate_csi / pre_div; in ccs_pll_calculate_vt_tree()
404 pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div; in ccs_pll_calculate_vt_tree()
429 div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div); in ccs_pll_calculate_vt_tree()
431 div = pre_div / div; in ccs_pll_calculate_vt_tree()
/drivers/clk/sophgo/
A Dclk-cv18xx-pll.c58 for_each_pll_limit_range(pre, &limit->pre_div) { in ipll_find_rate()
250 unsigned long pre_div, in fpll_find_synthesizer() argument
262 trate = fpll_calc_rate(parent, pre_div, div, post_div, in fpll_find_synthesizer()
297 for_each_pll_limit_range(pre, &limit->pre_div) { in fpll_find_rate()
A Dclk-cv18xx-pll.h15 } pre_div, div, post_div, ictrl, mode; member
A Dclk-cv1800.c41 .pre_div = _CV1800_PLL_LIMIT(1, 127),
48 .pre_div = _CV1800_PLL_LIMIT(1, 127),
/drivers/gpu/drm/bridge/
A Dti-sn65dsi86.c1433 unsigned int pre_div; in ti_sn_pwm_apply() local
1510 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, in ti_sn_pwm_apply()
1512 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; in ti_sn_pwm_apply()
1526 (u64)NSEC_PER_SEC * pre_div); in ti_sn_pwm_apply()
1530 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); in ti_sn_pwm_apply()
1562 unsigned int pre_div; in ti_sn_pwm_get_state() local
1579 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); in ti_sn_pwm_get_state()
1589 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), in ti_sn_pwm_get_state()
1591 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, in ti_sn_pwm_get_state()
/drivers/iio/adc/
A Dimx7d_adc.c126 u32 pre_div; member
131 .pre_div = (_pre_div), \
208 info->pre_div_num = adc_analogure_clk.pre_div; in imx7d_adc_sample_rate_set()
/drivers/atm/
A Deni.c1253 static const int pre_div[] = { 4,16,128,2048 }; in comp_tx() local
1262 if (TS_CLOCK/pre_div[*pre]/64 <= *pcr) break; in comp_tx()
1263 div = pre_div[*pre]**pcr; in comp_tx()
1272 if (TS_CLOCK/pre_div[*pre]/64 > -*pcr) break; in comp_tx()
1274 div = pre_div[*pre]*-*pcr; in comp_tx()
1281 *pcr = TS_CLOCK/pre_div[*pre]/(*res+1); in comp_tx()
/drivers/leds/rgb/
A Dleds-qcom-lpg.c1264 unsigned int pre_div; in lpg_pwm_get_state() local
1288 pre_div = lpg_pre_divs[FIELD_GET(PWM_FREQ_PRE_DIV_MASK, val)]; in lpg_pwm_get_state()
1296 pre_div * (1 << m), refclk); in lpg_pwm_get_state()
1297 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk); in lpg_pwm_get_state()

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