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Searched refs:psr_level (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
A Ddmub_psr.c230 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst) in dmub_psr_set_level() argument
245 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; in dmub_psr_set_level()
358 copy_settings_data->psr_level = psr_context->psr_level.u32all; in dmub_psr_copy_settings()
A Ddmub_psr.h46 void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level,
A Ddce_dmcu.c266 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; in dce_dmcu_setup_psr()
705 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; in dcn10_dmcu_setup_psr()
A Ddce_dmcu.h290 unsigned int psr_level:16; /*[15:0]*/ member
/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_edp_panel_control.c832 psr_context->psr_level.u32all = 0; in edp_setup_psr()
841 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; in edp_setup_psr()
844 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; in edp_setup_psr()
860 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1; in edp_setup_psr()
863 psr_context->psr_level.bits.DISABLE_ALPM = 0; in edp_setup_psr()
864 psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1; in edp_setup_psr()
/drivers/gpu/drm/amd/display/dc/
A Ddc_types.h717 union dmcu_psr_level psr_level; member
/drivers/gpu/drm/amd/display/dmub/inc/
A Ddmub_cmd.h3280 uint16_t psr_level; member
3437 uint16_t psr_level; member

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