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Searched refs:pstate (Results 1 – 25 of 80) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dbase.c316 pstate = (pstate < 0) ? clk->astate : pstate; in nvkm_pstate_work()
317 pstate = min(pstate, clk->state_nr - 1); in nvkm_pstate_work()
318 pstate = max(pstate, clk->dstate); in nvkm_pstate_work()
320 pstate = clk->pstate = -1; in nvkm_pstate_work()
324 if (pstate != clk->pstate) { in nvkm_pstate_work()
355 if (pstate->pstate != 0xff) in nvkm_pstate_info()
419 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); in nvkm_pstate_new()
425 pstate->pstate = perfE.pstate; in nvkm_pstate_new()
447 pstate->pstate, in nvkm_pstate_new()
483 if (pstate->pstate == req) in nvkm_clk_ustate_update()
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/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_plane.c636 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, in _dpu_plane_color_fill()
639 if (pstate->r_pipe.sspp) in _dpu_plane_color_fill()
640 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, in _dpu_plane_color_fill()
842 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; in dpu_plane_atomic_check_nosspp()
1198 pipe = &pstate->pipe; in dpu_plane_virtual_assign_resources()
1447 pstate->pending = true; in dpu_plane_sspp_atomic_update()
1462 &pstate->layout); in dpu_plane_sspp_atomic_update()
1548 if (!pstate) { in dpu_plane_duplicate_state()
1559 return &pstate->base; in dpu_plane_duplicate_state()
1641 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); in dpu_plane_reset()
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A Ddpu_crtc.c480 pstate->stage, in _dpu_crtc_blend_setup_mixer()
484 if (pstate->r_pipe.sspp) { in _dpu_crtc_blend_setup_mixer()
489 pstate->stage, in _dpu_crtc_blend_setup_mixer()
503 1 << pstate->stage; in _dpu_crtc_blend_setup_mixer()
1509 rc = PTR_ERR(pstate); in dpu_crtc_atomic_check()
1515 if (!pstate->visible) in dpu_crtc_atomic_check()
1632 if (!pstate || !state) in _dpu_debugfs_status_show()
1636 pstate->stage); in _dpu_debugfs_status_show()
1674 pstate->pipe.multirect_mode, pstate->pipe.multirect_index); in _dpu_debugfs_status_show()
1675 if (pstate->r_pipe.sspp) { in _dpu_debugfs_status_show()
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A Ddpu_core_perf.c44 struct dpu_plane_state *pstate; in _dpu_core_perf_calc_bw() local
49 pstate = to_dpu_plane_state(plane->state); in _dpu_core_perf_calc_bw()
50 if (!pstate) in _dpu_core_perf_calc_bw()
53 crtc_plane_bw += pstate->plane_fetch_bw; in _dpu_core_perf_calc_bw()
76 struct dpu_plane_state *pstate; in _dpu_core_perf_calc_clk() local
86 pstate = to_dpu_plane_state(plane->state); in _dpu_core_perf_calc_clk()
87 if (!pstate) in _dpu_core_perf_calc_clk()
90 crtc_clk = max(pstate->plane_clk, crtc_clk); in _dpu_core_perf_calc_clk()
/drivers/cpufreq/
A Dintel_pstate.c932 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) in show_base_frequency()
1233 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, in intel_pstate_get_hwp_cap()
2146 int_tofp(pstate - cpudata->pstate.min_pstate), in atom_get_val()
2152 if (pstate > cpudata->pstate.max_pstate) in atom_get_val()
2363 cpu->pstate.current_pstate = pstate; in intel_pstate_set_pstate()
2611 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; in get_target_pstate()
2641 if (pstate == cpu->pstate.current_pstate) in intel_pstate_update_pstate()
2644 cpu->pstate.current_pstate = pstate; in intel_pstate_update_pstate()
2882 cpu->pstate.max_freq : cpu->pstate.turbo_freq; in intel_pstate_get_max_freq()
3019 cpu->pstate.max_freq : cpu->pstate.turbo_freq; in intel_pstate_verify_cpu_policy()
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A Dbrcmstb-avs-cpufreq.c396 *pstate = args[0]; in brcm_avs_get_pstate()
405 args[0] = pstate; in brcm_avs_set_pstate()
429 unsigned int pstate; in brcm_avs_get_freq_table() local
433 ret = brcm_avs_get_pstate(priv, &pstate); in brcm_avs_get_freq_table()
456 ret = brcm_avs_set_pstate(priv, pstate); in brcm_avs_get_freq_table()
646 unsigned int pstate; in brcm_avs_cpufreq_init() local
648 ret = brcm_avs_get_pstate(priv, &pstate); in brcm_avs_cpufreq_init()
650 policy->cur = freq_table[pstate].frequency; in brcm_avs_cpufreq_init()
664 unsigned int pstate; in show_brcm_avs_pstate() local
666 if (brcm_avs_get_pstate(priv, &pstate)) in show_brcm_avs_pstate()
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A Dapple-soc-cpufreq.c140 unsigned int pstate; in apple_soc_cpufreq_get_rate() local
151 pstate = (reg & priv->info->cur_pstate_mask) >> priv->info->cur_pstate_shift; in apple_soc_cpufreq_get_rate()
159 pstate = FIELD_GET(APPLE_DVFS_CMD_PS1, reg); in apple_soc_cpufreq_get_rate()
163 if (p->driver_data == pstate) in apple_soc_cpufreq_get_rate()
167 pstate); in apple_soc_cpufreq_get_rate()
175 unsigned int pstate = policy->freq_table[index].driver_data; in apple_soc_cpufreq_set_target() local
189 reg |= pstate << priv->info->ps1_shift; in apple_soc_cpufreq_set_target()
192 reg |= FIELD_PREP(APPLE_DVFS_CMD_PS2, pstate); in apple_soc_cpufreq_set_target()
A DMakefile23 CFLAGS_amd-pstate-trace.o := -I$(src)
25 amd_pstate-y := amd-pstate.o amd-pstate-trace.o
36 obj-$(CONFIG_X86_AMD_PSTATE_UT) += amd-pstate-ut.o
/drivers/regulator/
A Dpwm-regulator.c86 struct pwm_state pstate; in pwm_regulator_set_voltage_sel() local
90 pwm_set_relative_duty_cycle(&pstate, in pwm_regulator_set_voltage_sel()
154 struct pwm_state pstate; in pwm_regulator_get_voltage() local
160 if (!pstate.enabled) { in pwm_regulator_get_voltage()
162 pstate.duty_cycle = pstate.period; in pwm_regulator_get_voltage()
164 pstate.duty_cycle = 0; in pwm_regulator_get_voltage()
201 struct pwm_state pstate; in pwm_regulator_set_voltage() local
328 struct pwm_state pstate; in pwm_regulator_init_boot_on() local
334 if (pstate.enabled) in pwm_regulator_init_boot_on()
343 pstate.duty_cycle = pstate.period; in pwm_regulator_init_boot_on()
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/drivers/gpu/drm/arm/
A Dmalidp_crtc.c259 const struct drm_plane_state *pstate; in malidp_crtc_atomic_check_scaling() local
286 pstate->src_w); in malidp_crtc_atomic_check_scaling()
288 pstate->src_h); in malidp_crtc_atomic_check_scaling()
294 s->input_w = pstate->src_h >> 16; in malidp_crtc_atomic_check_scaling()
295 s->input_h = pstate->src_w >> 16; in malidp_crtc_atomic_check_scaling()
297 s->input_w = pstate->src_w >> 16; in malidp_crtc_atomic_check_scaling()
298 s->input_h = pstate->src_h >> 16; in malidp_crtc_atomic_check_scaling()
301 s->output_w = pstate->crtc_w; in malidp_crtc_atomic_check_scaling()
302 s->output_h = pstate->crtc_h; in malidp_crtc_atomic_check_scaling()
348 const struct drm_plane_state *pstate; in malidp_crtc_atomic_check() local
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/drivers/pinctrl/sophgo/
A Dpinctrl-cv1800b.c40 u32 pstate = psmap[pin->power_domain]; in cv1800b_get_pull_up() local
47 if (pstate == PIN_POWER_STATE_1V8) in cv1800b_get_pull_up()
49 if (pstate == PIN_POWER_STATE_3V3) in cv1800b_get_pull_up()
61 u32 pstate = psmap[pin->power_domain]; in cv1800b_get_pull_down() local
68 if (pstate == PIN_POWER_STATE_1V8) in cv1800b_get_pull_down()
70 if (pstate == PIN_POWER_STATE_3V3) in cv1800b_get_pull_down()
118 u32 pstate = psmap[pin->power_domain]; in cv1800b_get_oc_map() local
126 if (pstate == PIN_POWER_STATE_1V8) { in cv1800b_get_oc_map()
129 } else if (pstate == PIN_POWER_STATE_3V3) { in cv1800b_get_oc_map()
164 u32 pstate = psmap[pin->power_domain]; in cv1800b_get_schmitt_map() local
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A Dpinctrl-sg2002.c40 u32 pstate = psmap[pin->power_domain]; in sg2002_get_pull_up() local
47 if (pstate == PIN_POWER_STATE_1V8) in sg2002_get_pull_up()
49 if (pstate == PIN_POWER_STATE_3V3) in sg2002_get_pull_up()
61 u32 pstate = psmap[pin->power_domain]; in sg2002_get_pull_down() local
68 if (pstate == PIN_POWER_STATE_1V8) in sg2002_get_pull_down()
70 if (pstate == PIN_POWER_STATE_3V3) in sg2002_get_pull_down()
118 u32 pstate = psmap[pin->power_domain]; in sg2002_get_oc_map() local
126 if (pstate == PIN_POWER_STATE_1V8) { in sg2002_get_oc_map()
129 } else if (pstate == PIN_POWER_STATE_3V3) { in sg2002_get_oc_map()
164 u32 pstate = psmap[pin->power_domain]; in sg2002_get_schmitt_map() local
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A Dpinctrl-cv1812h.c46 u32 pstate = psmap[pin->power_domain]; in cv1812h_get_pull_up() local
53 if (pstate == PIN_POWER_STATE_1V8) in cv1812h_get_pull_up()
55 if (pstate == PIN_POWER_STATE_3V3) in cv1812h_get_pull_up()
67 u32 pstate = psmap[pin->power_domain]; in cv1812h_get_pull_down() local
74 if (pstate == PIN_POWER_STATE_1V8) in cv1812h_get_pull_down()
76 if (pstate == PIN_POWER_STATE_3V3) in cv1812h_get_pull_down()
124 u32 pstate = psmap[pin->power_domain]; in cv1812h_get_oc_map() local
132 if (pstate == PIN_POWER_STATE_1V8) { in cv1812h_get_oc_map()
135 } else if (pstate == PIN_POWER_STATE_3V3) { in cv1812h_get_oc_map()
170 u32 pstate = psmap[pin->power_domain]; in cv1812h_get_schmitt_map() local
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A Dpinctrl-sg2000.c46 u32 pstate = psmap[pin->power_domain]; in sg2000_get_pull_up() local
53 if (pstate == PIN_POWER_STATE_1V8) in sg2000_get_pull_up()
55 if (pstate == PIN_POWER_STATE_3V3) in sg2000_get_pull_up()
67 u32 pstate = psmap[pin->power_domain]; in sg2000_get_pull_down() local
74 if (pstate == PIN_POWER_STATE_1V8) in sg2000_get_pull_down()
76 if (pstate == PIN_POWER_STATE_3V3) in sg2000_get_pull_down()
124 u32 pstate = psmap[pin->power_domain]; in sg2000_get_oc_map() local
132 if (pstate == PIN_POWER_STATE_1V8) { in sg2000_get_oc_map()
135 } else if (pstate == PIN_POWER_STATE_3V3) { in sg2000_get_oc_map()
170 u32 pstate = psmap[pin->power_domain]; in sg2000_get_schmitt_map() local
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/drivers/gpu/drm/nouveau/nvkm/engine/device/
A Dctrl.c55 args->v0.pstate = clk->pstate; in nvkm_control_mthd_pstate_info()
61 args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN; in nvkm_control_mthd_pstate_info()
75 struct nvkm_pstate *pstate; in nvkm_control_mthd_pstate_attr() local
106 list_for_each_entry(pstate, &clk->states, head) { in nvkm_control_mthd_pstate_attr()
111 lo = pstate->base.domain[domain->name]; in nvkm_control_mthd_pstate_attr()
113 list_for_each_entry(cstate, &pstate->list, head) { in nvkm_control_mthd_pstate_attr()
118 args->v0.state = pstate->pstate; in nvkm_control_mthd_pstate_attr()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_plane.c71 pstate->hwpipe->name : "(null)"); in mdp5_plane_atomic_print_state()
74 pstate->r_hwpipe ? pstate->r_hwpipe->name : in mdp5_plane_atomic_print_state()
123 kfree(pstate); in mdp5_plane_destroy_state()
960 if (WARN_ON(!pstate->hwpipe)) in mdp5_plane_pipe()
963 return pstate->hwpipe->pipe; in mdp5_plane_pipe()
970 if (!pstate->r_hwpipe) in mdp5_plane_right_pipe()
973 return pstate->r_hwpipe->pipe; in mdp5_plane_right_pipe()
981 if (WARN_ON(!pstate->hwpipe)) in mdp5_plane_get_flush()
984 mask = pstate->hwpipe->flush_mask; in mdp5_plane_get_flush()
986 if (pstate->r_hwpipe) in mdp5_plane_get_flush()
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A Dmdp5_crtc.c249 pstate = to_mdp5_plane_state(plane->state); in blend_setup()
250 pstates[pstate->stage] = pstate; in blend_setup()
257 r_stage[pstate->stage][PIPE_LEFT] = in blend_setup()
266 stage[pstate->stage][PIPE_RIGHT] = right_pipe; in blend_setup()
662 struct drm_plane_state *pstate) in is_fullscreen() argument
664 return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && in is_fullscreen()
665 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && in is_fullscreen()
666 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); in is_fullscreen()
704 const struct drm_plane_state *pstate; in mdp5_crtc_atomic_check() local
716 to_mdp5_plane_state(pstate); in mdp5_crtc_atomic_check()
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/drivers/gpu/drm/rockchip/
A Drockchip_drm_vop2.c439 struct drm_rect *src = &pstate->src; in vop2_afbc_transform_offset()
465 switch (pstate->rotation & in vop2_afbc_transform_offset()
713 struct drm_plane_state *pstate) in vop2_setup_csc_mode() argument
1026 if (!pstate->visible) in vop2_plane_atomic_check()
1038 pstate->visible = false; in vop2_plane_atomic_check()
1171 if (!pstate->visible) { in vop2_plane_atomic_update()
1913 if (!pstate || !pstate->fb) in vop2_plane_state_dump()
1916 fb = pstate->fb; in vop2_plane_state_dump()
1917 src = &pstate->src; in vop2_plane_state_dump()
1918 dst = &pstate->dst; in vop2_plane_state_dump()
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/drivers/net/wwan/
A Dwwan_hwsim.c64 } pstate; member
108 port->pstate = AT_PARSER_WAIT_A; in wwan_hwsim_port_start()
145 if (port->pstate == AT_PARSER_WAIT_A) { in wwan_hwsim_port_tx()
147 port->pstate = AT_PARSER_WAIT_T; in wwan_hwsim_port_tx()
149 port->pstate = AT_PARSER_SKIP_LINE; in wwan_hwsim_port_tx()
150 } else if (port->pstate == AT_PARSER_WAIT_T) { in wwan_hwsim_port_tx()
152 port->pstate = AT_PARSER_WAIT_TERM; in wwan_hwsim_port_tx()
154 port->pstate = AT_PARSER_SKIP_LINE; in wwan_hwsim_port_tx()
155 } else if (port->pstate == AT_PARSER_WAIT_TERM) { in wwan_hwsim_port_tx()
165 port->pstate = AT_PARSER_WAIT_A; in wwan_hwsim_port_tx()
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/drivers/gpu/drm/tve200/
A Dtve200_display.c72 struct drm_plane_state *pstate, in tve200_display_check() argument
77 struct drm_framebuffer *fb = pstate->fb; in tve200_display_check()
93 u32 offset = drm_fb_dma_get_gem_addr(fb, pstate, 0); in tve200_display_check()
265 struct drm_plane_state *pstate = plane->state; in tve200_display_update() local
266 struct drm_framebuffer *fb = pstate->fb; in tve200_display_update()
270 writel(drm_fb_dma_get_gem_addr(fb, pstate, 0), in tve200_display_update()
275 writel(drm_fb_dma_get_gem_addr(fb, pstate, 1), in tve200_display_update()
277 writel(drm_fb_dma_get_gem_addr(fb, pstate, 2), in tve200_display_update()
/drivers/thermal/intel/
A Dtherm_throt.c379 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); in therm_throt_process() local
384 state = &pstate->core_throttle; in therm_throt_process()
386 state = &pstate->core_power_limit; in therm_throt_process()
391 state = &pstate->package_throttle; in therm_throt_process()
393 state = &pstate->package_power_limit; in therm_throt_process()
439 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); in thresh_event_valid() local
443 state = (event == 0) ? &pstate->pkg_thresh0 : in thresh_event_valid()
444 &pstate->pkg_thresh1; in thresh_event_valid()
446 state = (event == 0) ? &pstate->core_thresh0 : in thresh_event_valid()
447 &pstate->core_thresh1; in thresh_event_valid()
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
A Dcstep.c78 info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5; in nvbios_cstepEp()
85 nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, in nvbios_cstepEm() argument
90 if (info->pstate == pstate) in nvbios_cstepEm()
A Dboost.c81 info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5; in nvbios_boostEp()
89 nvbios_boostEm(struct nvkm_bios *bios, u8 pstate, in nvbios_boostEm() argument
94 if (info->pstate == pstate) in nvbios_boostEm()
/drivers/pmdomain/apple/
A Dpmgr-pwrstate.c52 static int apple_pmgr_ps_set(struct generic_pm_domain *genpd, u32 pstate, bool auto_enable) in apple_pmgr_ps_set() argument
63 if (reg & APPLE_PMGR_RESET && pstate != APPLE_PMGR_PS_ACTIVE) in apple_pmgr_ps_set()
68 reg |= FIELD_PREP(APPLE_PMGR_PS_TARGET, pstate); in apple_pmgr_ps_set()
70 dev_dbg(ps->dev, "PS %s: pwrstate = 0x%x: 0x%x\n", genpd->name, pstate, reg); in apple_pmgr_ps_set()
76 (FIELD_GET(APPLE_PMGR_PS_ACTUAL, reg) == pstate), 1, in apple_pmgr_ps_set()
80 genpd->name, pstate, reg); in apple_pmgr_ps_set()
/drivers/gpu/drm/tidss/
A Dtidss_crtc.c134 struct drm_plane_state *pstate; in tidss_crtc_position_planes() local
139 for_each_new_plane_in_state(ostate, plane, pstate, i) { in tidss_crtc_position_planes()
140 if (pstate->crtc != crtc || !pstate->visible) in tidss_crtc_position_planes()
143 if (pstate->normalized_zpos == layer) { in tidss_crtc_position_planes()
154 pstate->crtc_x, pstate->crtc_y, in tidss_crtc_position_planes()

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