| /drivers/net/ethernet/intel/ice/ |
| A D | ice_parser_rt.c | 359 rt->pu.gpr_val_upd[idx] = true; in ice_gpr_add()
360 rt->pu.gpr_val[idx] = val; in ice_gpr_add()
378 rt->pu.flg_msk |= BIT_ULL(idx); in ice_flg_add()
380 rt->pu.flg_val |= BIT_ULL(idx); in ice_flg_add()
382 rt->pu.flg_val &= ~BIT_ULL(idx); in ice_flg_add()
441 rt->pu.err_msk |= (u16)BIT(idx); in ice_err_add()
562 struct ice_gpr_pu *pu = &rt->pu; in ice_pu_exe() local
568 if (pu->gpr_val_upd[i]) in ice_pu_exe()
573 if (pu->flg_msk & BIT(i)) in ice_pu_exe()
578 if (pu->err_msk & BIT(i)) in ice_pu_exe()
[all …]
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| A D | ice_parser.h | 439 struct ice_gpr_pu pu; member
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| /drivers/pinctrl/ |
| A D | pinctrl-eyeq5.c | 266 bool pd, pu; in eq5p_pinconf_get() local
269 pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); in eq5p_pinconf_get()
273 arg = !(pd || pu); in eq5p_pinconf_get()
279 arg = pu; in eq5p_pinconf_get()
310 bool pd, pu; in eq5p_pinctrl_pin_dbg_show() local
349 pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); in eq5p_pinctrl_pin_dbg_show()
350 if (pd && pu) in eq5p_pinctrl_pin_dbg_show()
352 else if (pd && !pu) in eq5p_pinctrl_pin_dbg_show()
354 else if (!pd && pu) in eq5p_pinctrl_pin_dbg_show()
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| A D | pinctrl-st.c | 233 struct regmap_field *alt, *oe, *pu, *od; member
248 const int alt, oe, pu, od, rt; member
350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
361 .pu = -1, /* Not Available */
386 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
583 if (pc->pu) { in st_pinconf_get_direction()
584 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
1147 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
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| /drivers/pinctrl/mediatek/ |
| A D | pinctrl-mtk-common-v2.c | 606 int err, pu, pd; in mtk_pinconf_bias_set_pu_pd() local
609 pu = 0; in mtk_pinconf_bias_set_pu_pd()
612 pu = 1; in mtk_pinconf_bias_set_pu_pd()
615 pu = 0; in mtk_pinconf_bias_set_pu_pd()
845 int pu, pd, rsel, err; in mtk_pinconf_bias_get_pu_pd_rsel() local
859 if (pu == 0 && pd == 0) { in mtk_pinconf_bias_get_pu_pd_rsel()
862 } else if (pu == 1 && pd == 0) { in mtk_pinconf_bias_get_pu_pd_rsel()
868 } else if (pu == 0 && pd == 1) { in mtk_pinconf_bias_get_pu_pd_rsel()
887 int err, pu, pd; in mtk_pinconf_bias_get_pu_pd() local
897 if (pu == 0 && pd == 0) { in mtk_pinconf_bias_get_pu_pd()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| A D | gm200.c | 34 gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gm200_sor_dp_drive() argument
41 pu &= 0x0f; in gm200_sor_dp_drive()
46 if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0) in gm200_sor_dp_drive()
47 data[2] = (data[2] & ~0x00000f00) | (pu << 8); in gm200_sor_dp_drive()
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| A D | g94.c | 64 g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in g94_sor_dp_drive() argument
74 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in g94_sor_dp_drive()
75 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in g94_sor_dp_drive()
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| A D | outp.h | 109 int (*aux_pwr)(struct nvkm_outp *, bool pu);
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| A D | nv50.c | 80 nv50_pior_power(struct nvkm_ior *pior, bool normal, bool pu, bool data, bool vsync, bool hsync) in nv50_pior_power() argument
85 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift; in nv50_pior_power()
212 nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, bool data, bool vsync, bool hsync) in nv50_sor_power() argument
217 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift; in nv50_sor_power()
313 nv50_dac_power(struct nvkm_ior *dac, bool normal, bool pu, bool data, bool vsync, bool hsync) in nv50_dac_power() argument
318 const u32 state = 0x80000000 | (0x00000040 * ! pu | in nv50_dac_power()
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| A D | gf119.c | 129 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gf119_sor_dp_drive() argument
139 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in gf119_sor_dp_drive()
140 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in gf119_sor_dp_drive()
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| A D | ior.h | 59 void (*power)(struct nvkm_ior *, bool normal, bool pu,
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| A D | dp.c | 71 nvkm_dp_aux_pwr(struct nvkm_outp *outp, bool pu) in nvkm_dp_aux_pwr() argument
73 outp->dp.enabled = pu; in nvkm_dp_aux_pwr()
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| /drivers/regulator/ |
| A D | max77620-regulator.c | 170 int pu = rpdata->active_fps_pu_slot; in max77620_regulator_set_fps_slots() local
178 pu = rpdata->suspend_fps_pu_slot; in max77620_regulator_set_fps_slots()
183 if (pu >= 0) { in max77620_regulator_set_fps_slots()
184 val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT); in max77620_regulator_set_fps_slots()
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| /drivers/pinctrl/bcm/ |
| A D | pinctrl-ns2-mux.c | 164 #define NS2_PIN_DESC(p, n, b, o, s, i, pu, d) \ argument
173 .pull_shift = pu, \
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| /drivers/pinctrl/nuvoton/ |
| A D | pinctrl-npcm7xx.c | 1692 u32 ie, oe, pu, pd; in npcm7xx_config_get() local
1699 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; in npcm7xx_config_get()
1702 rc = (!pu && !pd); in npcm7xx_config_get()
1704 rc = (pu && !pd); in npcm7xx_config_get()
1706 rc = (!pu && pd); in npcm7xx_config_get()
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| A D | pinctrl-npcm8xx.c | 2177 u32 ie, oe, pu, pd; in npcm8xx_config_get() local
2184 pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask; in npcm8xx_config_get()
2187 rc = !pu && !pd; in npcm8xx_config_get()
2189 rc = pu && !pd; in npcm8xx_config_get()
2191 rc = !pu && pd; in npcm8xx_config_get()
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| /drivers/of/ |
| A D | property.c | 593 u32 *pu) in of_prop_next_u32() argument
610 *pu = be32_to_cpup(curv); in of_prop_next_u32()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ |
| A D | disp.c | 1122 r535_dp_aux_pwr(struct nvkm_outp *outp, bool pu) in r535_dp_aux_pwr() argument
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