| /drivers/gpu/drm/amd/display/dc/hubp/dcn21/ |
| A D | dcn21_hubp.c | 501 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, in hubp21_validate_dml_output()
535 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) in hubp21_validate_dml_output()
537 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); in hubp21_validate_dml_output()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.c | 165 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, in hubp2_program_deadline()
1610 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, in hubp2_validate_dml_output()
1644 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) in hubp2_validate_dml_output()
1646 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); in hubp2_validate_dml_output()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_dchub_registers.h | 75 uint32_t qos_level_fixed_cur0; member
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_rq_dlg_helpers.c | 371 ttu_regs->qos_level_fixed_cur0); in print__ttu_regs_st()
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| A D | display_mode_structs.h | 690 unsigned int qos_level_fixed_cur0; member
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| A D | dml1_display_rq_dlg_calc.c | 1912 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml1_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 317 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0, in dcn10_get_ttu_states()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_rq_dlg_calc_32.c | 548 ttu_regs->qos_level_fixed_cur0 = 8; in dml32_rq_dlg_get_dlg_reg()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml_display_rq_dlg_calc.c | 497 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml_rq_dlg_get_dlg_reg()
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| A D | dml2_translation_helper.c | 1519 out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0; in dml2_update_pipe_ctx_dchub_regs()
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| A D | display_mode_util.c | 320 dml_print("DML: qos_level_fixed_cur0 = 0x%x\n", ttu_regs->qos_level_fixed_cur0); in dml_print_ttu_regs_st()
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| A D | display_mode_core_structs.h | 1995 dml_uint_t qos_level_fixed_cur0; member
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 298 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, in hubp401_program_deadline()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 690 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, in hubp1_program_deadline()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 1517 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml20_rq_dlg_get_dlg_params()
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| A D | display_rq_dlg_calc_20v2.c | 1518 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml20v2_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 1625 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 1714 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 1531 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 1619 disp_ttu_regs->qos_level_fixed_cur0 = 8; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 432 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0, in dcn10_log_hubp_states()
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