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Searched refs:quad_part (Results 1 – 25 of 37) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c90 if (hwseq->fb_base.quad_part <= addr->quad_part && in gpu_addr_to_uma()
91 addr->quad_part < hwseq->fb_top.quad_part) { in gpu_addr_to_uma()
92 addr->quad_part -= hwseq->fb_base.quad_part; in gpu_addr_to_uma()
93 addr->quad_part += hwseq->fb_offset.quad_part; in gpu_addr_to_uma()
95 } else if (hwseq->fb_offset.quad_part <= addr->quad_part && in gpu_addr_to_uma()
96 addr->quad_part <= hwseq->uma_top.quad_part) { in gpu_addr_to_uma()
213 hws->fb_base.quad_part <<= 24; in read_mmhub_vm_setup()
216 hws->fb_top.quad_part <<= 24; in read_mmhub_vm_setup()
220 hws->uma_top.quad_part = hws->fb_top.quad_part in read_mmhub_vm_setup()
221 - hws->fb_base.quad_part + hws->fb_offset.quad_part; in read_mmhub_vm_setup()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c54 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; in hubp3_set_vm_system_aperture_settings()
55 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; in hubp3_set_vm_system_aperture_settings()
58 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); in hubp3_set_vm_system_aperture_settings()
108 if (address->grph.addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
115 if (address->grph.meta_addr.quad_part != 0) { in hubp3_program_surface_flip_and_addr()
134 if (address->video_progressive.luma_addr.quad_part == 0 in hubp3_program_surface_flip_and_addr()
179 if (address->grph_stereo.left_addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
181 if (address->grph_stereo.right_addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
264 if (address->rgbea.addr.quad_part == 0 in hubp3_program_surface_flip_and_addr()
265 || address->rgbea.alpha_addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c388 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
395 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
414 if (address->video_progressive.luma_addr.quad_part == 0 in hubp1_program_surface_flip_and_addr()
459 if (address->grph_stereo.left_addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
461 if (address->grph_stereo.right_addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
484 if (address->grph_stereo.left_meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
773 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
790 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; in hubp1_set_vm_system_aperture_settings()
791 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; in hubp1_set_vm_system_aperture_settings()
792 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; in hubp1_set_vm_system_aperture_settings()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
A Ddcn21_hubp.c239 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; in hubp21_set_vm_system_aperture_settings()
240 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; in hubp21_set_vm_system_aperture_settings()
243 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); in hubp21_set_vm_system_aperture_settings()
246 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); in hubp21_set_vm_system_aperture_settings()
709 if (address->grph.addr.quad_part == 0) { in hubp21_program_surface_flip_and_addr()
714 if (address->grph.meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
727 if (address->video_progressive.luma_addr.quad_part == 0 in hubp21_program_surface_flip_and_addr()
756 if (address->grph_stereo.left_addr.quad_part == 0) in hubp21_program_surface_flip_and_addr()
758 if (address->grph_stereo.right_addr.quad_part == 0) in hubp21_program_surface_flip_and_addr()
763 if (address->grph_stereo.right_meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c57 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; in hubp2_set_vm_system_aperture_settings()
60 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; in hubp2_set_vm_system_aperture_settings()
61 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; in hubp2_set_vm_system_aperture_settings()
71 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); in hubp2_set_vm_system_aperture_settings()
756 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
763 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
782 if (address->video_progressive.luma_addr.quad_part == 0 in hubp2_program_surface_flip_and_addr()
827 if (address->grph_stereo.left_addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
829 if (address->grph_stereo.right_addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
945 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp2_is_flip_pending()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c412 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) in dcn316_notify_wm_ranges()
434 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn316_get_dpm_table_from_smu()
604 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn316_clk_mgr_construct()
608 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
616 &smu_dpm_clks.mc_address.quad_part); in dcn316_clk_mgr_construct()
620 smu_dpm_clks.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
668 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn316_clk_mgr_construct()
677 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn316_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c451 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) in vg_notify_wm_ranges()
649 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in vg_get_dpm_table_from_smu()
687 &clk_mgr->smu_wm_set.mc_address.quad_part); in vg_clk_mgr_construct()
691 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in vg_clk_mgr_construct()
699 &smu_dpm_clks.mc_address.quad_part); in vg_clk_mgr_construct()
703 smu_dpm_clks.mc_address.quad_part = 0; in vg_clk_mgr_construct()
741 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in vg_clk_mgr_construct()
750 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in vg_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c488 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 && in dcn30_mmhubbub_warmup()
493 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part; in dcn30_mmhubbub_warmup()
513 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf]; in dcn30_mmhubbub_warmup()
893 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { in dcn30_program_dmdata_engine()
951 plane->address.grph.cursor_cache_addr.quad_part; in dcn30_apply_idle_power_optimizations()
969 plane->address.page_table_base.quad_part == 0 && in dcn30_apply_idle_power_optimizations()
1057 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; in dcn30_apply_idle_power_optimizations()
1058 cmd.mall.cursor_copy_dst.quad_part = in dcn30_apply_idle_power_optimizations()
1059 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; in dcn30_apply_idle_power_optimizations()
1067 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part; in dcn30_apply_idle_power_optimizations()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c447 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0) in dcn315_notify_wm_ranges()
469 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn315_get_dpm_table_from_smu()
630 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn315_clk_mgr_construct()
634 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
642 &smu_dpm_clks.mc_address.quad_part); in dcn315_clk_mgr_construct()
646 smu_dpm_clks.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
725 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn315_clk_mgr_construct()
734 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn315_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c486 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()
508 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn31_get_dpm_table_from_smu()
699 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()
703 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
711 &smu_dpm_clks.mc_address.quad_part); in dcn31_clk_mgr_construct()
715 smu_dpm_clks.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
797 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn31_clk_mgr_construct()
806 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn31_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c811 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0) in dcn35_notify_wm_ranges()
833 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn35_get_dpm_table_from_smu()
852 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn351_get_dpm_table_from_smu()
1281 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn35_clk_mgr_construct()
1285 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn35_clk_mgr_construct()
1293 &smu_dpm_clks.mc_address.quad_part); in dcn35_clk_mgr_construct()
1296 smu_dpm_clks.mc_address.quad_part = 0; in dcn35_clk_mgr_construct()
1305 &smu_dpm_clks_dcn351.mc_address.quad_part); in dcn35_clk_mgr_construct()
1308 smu_dpm_clks_dcn351.mc_address.quad_part = 0; in dcn35_clk_mgr_construct()
1401 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn35_clk_mgr_construct()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c550 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) in dcn314_notify_wm_ranges()
572 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn314_get_dpm_table_from_smu()
809 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn314_clk_mgr_construct()
813 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()
821 &smu_dpm_clks.mc_address.quad_part); in dcn314_clk_mgr_construct()
825 smu_dpm_clks.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()
907 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn314_clk_mgr_construct()
916 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn314_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c405 if (address->grph.addr.quad_part == 0) in hubp401_program_surface_flip_and_addr()
420 if (address->video_progressive.luma_addr.quad_part == 0 in hubp401_program_surface_flip_and_addr()
421 || address->video_progressive.chroma_addr.quad_part == 0) in hubp401_program_surface_flip_and_addr()
445 if (address->grph_stereo.left_addr.quad_part == 0) in hubp401_program_surface_flip_and_addr()
447 if (address->grph_stereo.right_addr.quad_part == 0) in hubp401_program_surface_flip_and_addr()
489 if (address->rgbea.addr.quad_part == 0 in hubp401_program_surface_flip_and_addr()
490 || address->rgbea.alpha_addr.quad_part == 0) in hubp401_program_surface_flip_and_addr()
725 if (hubp->curs_attr.address.quad_part == 0) in hubp401_cursor_set_position()
/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
A Ddcn32_mmhubbub.c80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub32_warmup_mcif()
/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.c80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub3_warmup_mcif()
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn30.c84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn30_translate_addr()
A Ddmub_srv.c682 cw0.offset.quad_part = inst_fb->gpu_addr; in dmub_srv_hw_init()
686 cw1.offset.quad_part = stack_fb->gpu_addr; in dmub_srv_hw_init()
708 cw2.offset.quad_part = data_fb->gpu_addr; in dmub_srv_hw_init()
712 cw3.offset.quad_part = bios_fb->gpu_addr; in dmub_srv_hw_init()
716 cw4.offset.quad_part = mail_fb->gpu_addr; in dmub_srv_hw_init()
732 cw5.offset.quad_part = tracebuff_fb->gpu_addr; in dmub_srv_hw_init()
739 cw6.offset.quad_part = fw_state_fb->gpu_addr; in dmub_srv_hw_init()
745 region6.offset.quad_part = shared_state_fb->gpu_addr; in dmub_srv_hw_init()
A Ddmub_dcn20.c84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn20_translate_addr()
A Ddmub_dcn31.c80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn31_translate_addr()
A Ddmub_dcn35.c85 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn35_translate_addr()
A Ddmub_dcn32.c86 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn32_translate_addr()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c72 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
73 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddmub_abm_lcd.c178 …cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_ad… in dmub_abm_init_config()
238 …cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_a… in dmub_abm_save_restore()
A Ddce_mem_input.c871 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
876 if (address->grph_stereo.left_addr.quad_part == 0 || in dce_mi_program_surface_flip_and_addr()
877 address->grph_stereo.right_addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/inc/
A Dcompressor.h45 uint64_t quad_part; member

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