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Searched refs:range_min_qp (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc_1_2.c289 (rc[0].range_min_qp << 0) | in dpu_hw_dsc_config_thresh_1_2()
290 (rc[1].range_min_qp << 5) | in dpu_hw_dsc_config_thresh_1_2()
291 (rc[2].range_min_qp << 10) | in dpu_hw_dsc_config_thresh_1_2()
292 (rc[3].range_min_qp << 15) | in dpu_hw_dsc_config_thresh_1_2()
293 (rc[4].range_min_qp << 20)); in dpu_hw_dsc_config_thresh_1_2()
308 (rc[5].range_min_qp << 0) | in dpu_hw_dsc_config_thresh_1_2()
309 (rc[6].range_min_qp << 5) | in dpu_hw_dsc_config_thresh_1_2()
310 (rc[7].range_min_qp << 10) | in dpu_hw_dsc_config_thresh_1_2()
311 (rc[8].range_min_qp << 15) | in dpu_hw_dsc_config_thresh_1_2()
312 (rc[9].range_min_qp << 20)); in dpu_hw_dsc_config_thresh_1_2()
[all …]
A Ddpu_hw_dsc.c144 DPU_REG_WRITE(c, off, rc[i].range_min_qp); in dpu_hw_dsc_config_thresh()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c329 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, in dsc_write_to_registers()
334 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, in dsc_write_to_registers()
337 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, in dsc_write_to_registers()
342 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, in dsc_write_to_registers()
345 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, in dsc_write_to_registers()
350 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, in dsc_write_to_registers()
353 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, in dsc_write_to_registers()
358 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, in dsc_write_to_registers()
361 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, in dsc_write_to_registers()
366 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c248 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << in drm_dsc_pps_payload_pack()
1286 vdsc_cfg->rc_range_params[i].range_min_qp = in drm_dsc_setup_rc_params()
1287 rc_params->rc_range_params[i].range_min_qp; in drm_dsc_setup_rc_params()
1534 rp[0].range_min_qp, rp[1].range_min_qp, rp[2].range_min_qp, rp[3].range_min_qp, in drm_dsc_dump_config_rc_params()
1535 rp[4].range_min_qp, rp[5].range_min_qp, rp[6].range_min_qp, rp[7].range_min_qp, in drm_dsc_dump_config_rc_params()
1536 rp[8].range_min_qp, rp[9].range_min_qp, rp[10].range_min_qp, rp[11].range_min_qp, in drm_dsc_dump_config_rc_params()
1537 rp[12].range_min_qp, rp[13].range_min_qp, rp[14].range_min_qp); in drm_dsc_dump_config_rc_params()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c707 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, in dsc_write_to_registers()
712 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, in dsc_write_to_registers()
715 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, in dsc_write_to_registers()
720 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, in dsc_write_to_registers()
723 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, in dsc_write_to_registers()
728 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, in dsc_write_to_registers()
731 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, in dsc_write_to_registers()
736 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, in dsc_write_to_registers()
739 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, in dsc_write_to_registers()
744 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/dsc/
A Ddscc_types.h36 int range_min_qp; member
A Drc_calc_dpi.c84 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; in copy_rc_to_cfg()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c63 vdsc_cfg->rc_range_params[buf].range_min_qp = in intel_vdsc_set_min_max_qp()
620 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()

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