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Searched refs:ras_block (Results 1 – 25 of 53) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_nbio.c34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
66 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_nbio_ras_late_init() argument
69 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_nbio_ras_late_init()
73 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_nbio_ras_late_init()
84 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_nbio_ras_late_init()
A Damdgpu_umc.c109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
300 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in amdgpu_umc_ras_sw_init()
301 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in amdgpu_umc_ras_sw_init()
303 adev->umc.ras_if = &ras->ras_block.ras_comm; in amdgpu_umc_ras_sw_init()
305 if (!ras->ras_block.ras_late_init) in amdgpu_umc_ras_sw_init()
308 if (!ras->ras_block.ras_cb) in amdgpu_umc_ras_sw_init()
309 ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in amdgpu_umc_ras_sw_init()
318 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_umc_ras_late_init()
325 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_umc_ras_late_init()
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A Damdgpu_mmhub.c33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
A Damdgpu_hdp.c36 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_hdp_ras_sw_init()
42 strcpy(ras->ras_block.ras_comm.name, "hdp"); in amdgpu_hdp_ras_sw_init()
43 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP; in amdgpu_hdp_ras_sw_init()
44 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_hdp_ras_sw_init()
45 adev->hdp.ras_if = &ras->ras_block.ras_comm; in amdgpu_hdp_ras_sw_init()
A Damdgpu_mca.c94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
118 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp1_ras_sw_init()
124 strcpy(ras->ras_block.ras_comm.name, "mca.mp1"); in amdgpu_mca_mp1_ras_sw_init()
125 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp1_ras_sw_init()
127 adev->mca.mp1.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp1_ras_sw_init()
148 strcpy(ras->ras_block.ras_comm.name, "mca.mpio"); in amdgpu_mca_mpio_ras_sw_init()
149 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mpio_ras_sw_init()
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A Damdgpu_sdma.c94 struct ras_common_if *ras_block) in amdgpu_sdma_ras_late_init() argument
98 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_sdma_ras_late_init()
102 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_sdma_ras_late_init()
114 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_sdma_ras_late_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
333 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
336 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
337 ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; in amdgpu_sdma_ras_sw_init()
340 if (!ras->ras_block.ras_cb) in amdgpu_sdma_ras_sw_init()
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A Damdgpu_jpeg.c285 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_jpeg_ras_late_init() argument
289 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_jpeg_ras_late_init()
293 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_jpeg_ras_late_init()
307 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_jpeg_ras_late_init()
320 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
326 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
327 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
328 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
329 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
331 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
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A Dmca_v3_0.c60 .ras_block = {
80 .ras_block = {
100 .ras_block = {
A Daldebaran.c378 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
379 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
380 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
388 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
389 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
390 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
A Damdgpu_ras.c99 if (!ras_block) in get_ras_block_str()
106 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) in get_ras_block_str()
109 return ras_block_string[ras_block->block]; in get_ras_block_str()
4111 struct ras_common_if *ras_block) in amdgpu_persistent_edc_harvesting() argument
4114 .head = *ras_block, in amdgpu_persistent_edc_harvesting()
4141 struct ras_common_if *ras_block) in amdgpu_ras_block_late_init() argument
4214 struct ras_common_if *ras_block) in amdgpu_ras_block_late_init_default() argument
4221 struct ras_common_if *ras_block) in amdgpu_ras_block_late_fini() argument
4224 if (!ras_block) in amdgpu_ras_block_late_fini()
4227 amdgpu_ras_sysfs_remove(adev, ras_block); in amdgpu_ras_block_late_fini()
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A Damdgpu_gfx.c926 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_gfx_ras_late_init()
933 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_gfx_ras_late_init()
946 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); in amdgpu_gfx_ras_late_init()
951 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_gfx_ras_late_init()
974 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
975 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; in amdgpu_gfx_ras_sw_init()
977 adev->gfx.ras_if = &ras->ras_block.ras_comm; in amdgpu_gfx_ras_sw_init()
980 if (!ras->ras_block.ras_late_init) in amdgpu_gfx_ras_sw_init()
984 if (!ras->ras_block.ras_cb) in amdgpu_gfx_ras_sw_init()
985 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; in amdgpu_gfx_ras_sw_init()
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A Damdgpu_nbio.h51 struct amdgpu_ras_block_object ras_block; member
119 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
A Damdgpu_ras.h712 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
713 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
837 struct ras_common_if *ras_block);
840 struct ras_common_if *ras_block);
901 const char *get_ras_block_str(struct ras_common_if *ras_block);
A Damdgpu_sdma.h109 struct amdgpu_ras_block_object ras_block; member
186 struct ras_common_if *ras_block);
A Damdgpu_vcn.c1261 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_vcn_ras_late_init() argument
1265 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_vcn_ras_late_init()
1269 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_vcn_ras_late_init()
1283 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_vcn_ras_late_init()
1296 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1302 strcpy(ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_ras_sw_init()
1303 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1304 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_ras_sw_init()
1305 adev->vcn.ras_if = &ras->ras_block.ras_comm; in amdgpu_vcn_ras_sw_init()
1307 if (!ras->ras_block.ras_late_init) in amdgpu_vcn_ras_sw_init()
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A Damdgpu_jpeg.h121 struct amdgpu_ras_block_object ras_block; member
162 struct ras_common_if *ras_block);
A Damdgpu_umc.h97 struct amdgpu_ras_block_object ras_block; member
153 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
A Damdgpu_xgmi.c1224 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_xgmi_ras_late_init() argument
1234 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_xgmi_ras_late_init()
1253 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_xgmi_ras_late_init()
1614 .ras_block = {
1629 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1635 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); in amdgpu_xgmi_ras_sw_init()
1636 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; in amdgpu_xgmi_ras_sw_init()
1637 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_xgmi_ras_sw_init()
1638 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; in amdgpu_xgmi_ras_sw_init()
A Damdgpu_hdp.h28 struct amdgpu_ras_block_object ras_block; member
A Damdgpu_mmhub.h48 struct amdgpu_ras_block_object ras_block; member
A Djpeg_v5_0_1.c1053 static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in jpeg_v5_0_1_ras_late_init() argument
1057 r = amdgpu_ras_block_late_init(adev, ras_block); in jpeg_v5_0_1_ras_late_init()
1061 if (amdgpu_ras_is_supported(adev, ras_block->block) && in jpeg_v5_0_1_ras_late_init()
1076 amdgpu_ras_block_late_fini(adev, ras_block); in jpeg_v5_0_1_ras_late_init()
1082 .ras_block = {
A Dmmhub_v1_8.c845 static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in mmhub_v1_8_ras_late_init() argument
849 r = amdgpu_ras_block_late_init(adev, ras_block); in mmhub_v1_8_ras_late_init()
861 amdgpu_ras_block_late_fini(adev, ras_block); in mmhub_v1_8_ras_late_init()
867 .ras_block = {
A Damdgpu_xgmi.h74 struct amdgpu_ras_block_object ras_block; member
A Dumc_v12_0.c508 static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in umc_v12_0_ras_late_init() argument
512 ret = amdgpu_umc_ras_late_init(adev, ras_block); in umc_v12_0_ras_late_init()
712 .ras_block = {
A Dumc_v8_14.c156 .ras_block = {

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