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Searched refs:rate (Results 1 – 25 of 1349) sorted by relevance

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/drivers/mmc/host/
A Dsdhci-of-aspeed-test.c8 int rate = 52000000; in aspeed_sdhci_phase_ddr52() local
11 aspeed_sdhci_phase_to_tap(NULL, rate, 0)); in aspeed_sdhci_phase_ddr52()
13 aspeed_sdhci_phase_to_tap(NULL, rate, 1)); in aspeed_sdhci_phase_ddr52()
15 aspeed_sdhci_phase_to_tap(NULL, rate, 2)); in aspeed_sdhci_phase_ddr52()
17 aspeed_sdhci_phase_to_tap(NULL, rate, 3)); in aspeed_sdhci_phase_ddr52()
19 aspeed_sdhci_phase_to_tap(NULL, rate, 4)); in aspeed_sdhci_phase_ddr52()
21 aspeed_sdhci_phase_to_tap(NULL, rate, 5)); in aspeed_sdhci_phase_ddr52()
23 aspeed_sdhci_phase_to_tap(NULL, rate, 23)); in aspeed_sdhci_phase_ddr52()
25 aspeed_sdhci_phase_to_tap(NULL, rate, 24)); in aspeed_sdhci_phase_ddr52()
27 aspeed_sdhci_phase_to_tap(NULL, rate, 25)); in aspeed_sdhci_phase_ddr52()
[all …]
/drivers/clk/rockchip/
A Dclk-pll.c57 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
202 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
324 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
437 __func__, rate->rate, rate->nr, rate->no, rate->nf); in rockchip_rk3066_pll_set_params()
554 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); in rockchip_rk3066_pll_init()
685 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
686 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
807 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3399_pll_init()
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/drivers/clk/actions/
A Dowl-composite.c60 long rate; in owl_comp_div_determine_rate() local
62 rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw, in owl_comp_div_determine_rate()
64 if (rate < 0) in owl_comp_div_determine_rate()
65 return rate; in owl_comp_div_determine_rate()
67 req->rate = rate; in owl_comp_div_determine_rate()
86 rate, parent_rate); in owl_comp_div_set_rate()
93 long rate; in owl_comp_fact_determine_rate() local
98 if (rate < 0) in owl_comp_fact_determine_rate()
99 return rate; in owl_comp_fact_determine_rate()
101 req->rate = rate; in owl_comp_fact_determine_rate()
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A Dowl-factor.c54 if ((unsigned long)calc_rate <= rate) { in _get_table_val()
67 struct clk_hw *hw, unsigned long rate, in owl_clk_val_best() argument
75 if (!rate) in owl_clk_val_best()
76 rate = 1; in owl_clk_val_best()
121 unsigned long rate, in owl_factor_helper_round_rate() argument
140 rate, parent_rate); in owl_factor_round_rate()
148 unsigned long long int rate; in owl_factor_helper_recalc_rate() local
168 do_div(rate, div); in owl_factor_helper_recalc_rate()
170 return rate; in owl_factor_helper_recalc_rate()
185 unsigned long rate, in owl_factor_helper_set_rate() argument
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/drivers/net/wireless/intel/iwlwifi/mvm/
A Drs.c529 rate->sgi, rate->ldpc, rate->stbc); in rs_dump_rate()
825 if (is_siso(rate) && rate->stbc) { in ucode_rate_from_rs_rate()
849 memset(rate, 0, sizeof(*rate)); in rs_rate_from_ucode_rate()
891 rate->stbc, rate->bfer); in rs_rate_from_ucode_rate()
905 rate->stbc, rate->bfer); in rs_rate_from_ucode_rate()
1126 if (rate->ant == ANT_A || rate->stbc || rate->bfer) in rs_get_column_from_rate()
2090 rate = &tbl->rate; in rs_rate_scale_perform()
2657 rate = &tbl->rate; in rs_initialize_lq()
3877 rate = &tbl->rate; in rs_sta_dbgfs_stats_table_read()
3958 for (rate = 0; rate < IWL_RATE_COUNT; rate++) in rs_sta_dbgfs_drv_tx_stats_read()
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A Drs.h179 #define is_legacy(rate) is_type_legacy((rate)->type) argument
180 #define is_ht_siso(rate) is_type_ht_siso((rate)->type) argument
181 #define is_ht_mimo2(rate) is_type_ht_mimo2((rate)->type) argument
184 #define is_siso(rate) is_type_siso((rate)->type) argument
185 #define is_mimo2(rate) is_type_mimo2((rate)->type) argument
186 #define is_mimo(rate) is_type_mimo((rate)->type) argument
187 #define is_ht(rate) is_type_ht((rate)->type) argument
188 #define is_vht(rate) is_type_vht((rate)->type) argument
189 #define is_he(rate) is_type_he((rate)->type) argument
190 #define is_a_band(rate) is_type_a_band((rate)->type) argument
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/drivers/clk/
A Dclk_test.c82 ctx->rate = rate; in clk_dummy_set_rate()
235 KUNIT_EXPECT_EQ(test, rate, ctx->rate); in clk_test_get_rate()
865 long rate; in clk_test_orphan_transparent_multiple_parent_mux_set_range_round_rate() local
1096 long rate; in clk_test_single_parent_mux_set_range_round_rate_parent_only() local
1126 long rate; in clk_test_single_parent_mux_set_range_round_rate_child_smaller() local
1164 long rate; in clk_test_single_parent_mux_set_range_round_rate_parent_smaller() local
1512 long rate; in clk_range_test_set_range_round_rate_lower() local
1597 long rate; in clk_range_test_set_range_round_rate_higher() local
2152 req->rate = parent_req->rate; in clk_leaf_mux_determine_rate()
3126 ctx->rate = rate; in clk_assigned_rates_register_clk()
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A Dclk-cdce925.c102 if (rate <= parent_rate) { in cdce925_pll_find_rate()
115 un = rate / g; in cdce925_pll_find_rate()
145 if (!rate || (rate == parent_rate)) { in cdce925_pll_set_rate()
157 if (rate < parent_rate) { in cdce925_pll_set_rate()
159 rate, parent_rate); in cdce925_pll_set_rate()
190 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); in cdce925_pll_calc_range_bits()
191 if (rate >= 175000000) in cdce925_pll_calc_range_bits()
193 if (rate >= 150000000) in cdce925_pll_calc_range_bits()
195 if (rate >= 125000000) in cdce925_pll_calc_range_bits()
368 if (!rate) in cdce925_calc_divider()
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A Dclk-vt8500.c137 if (rate == 0) in vt8500_dclk_round_rate()
140 divisor = *prate / rate; in vt8500_dclk_round_rate()
164 if (rate == 0) in vt8500_dclk_set_rate()
356 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
371 if (tclk != rate) in vt8500_find_pll_bits()
373 rate, tclk); in vt8500_find_pll_bits()
395 if (!parent_rate || (rate < 37500000) || (rate > 600000000)) in wm8650_find_pll_bits()
398 *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 : in wm8650_find_pll_bits()
466 if (tclk > rate) in wm8750_find_pll_bits()
493 rate - best_err); in wm8750_find_pll_bits()
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A Dclk-sparx5.c68 rate = mult_frac(rate, divt, divb); in s5_calc_freq()
69 rate = roundup(rate, 1000); in s5_calc_freq()
72 return rate; in s5_calc_freq()
112 if (parent_rate % rate) { in s5_calc_params()
120 if (alt1.freq == rate) { in s5_calc_params()
124 div = parent_rate / rate; in s5_calc_params()
129 if (abs(rate - alt1.freq) < in s5_calc_params()
130 abs(rate - alt2.freq)) in s5_calc_params()
139 conf->div = parent_rate / rate; in s5_calc_params()
166 unsigned long rate, in s5_pll_set_rate() argument
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A Dclk-fractional-divider_test.c19 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; in clk_fd_test_approximation_max_denominator() local
28 rate = 240000000; in clk_fd_test_approximation_max_denominator()
29 parent_rate = (max_n + 1) * rate; /* so that it exceeds the maximum divisor */ in clk_fd_test_approximation_max_denominator()
32 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n); in clk_fd_test_approximation_max_denominator()
48 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; in clk_fd_test_approximation_max_numerator() local
57 rate = 240000000; in clk_fd_test_approximation_max_numerator()
77 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; in clk_fd_test_approximation_max_denominator_zero_based() local
87 rate = 240000000; in clk_fd_test_approximation_max_denominator_zero_based()
88 parent_rate = (max_n + 1) * rate; /* so that it exceeds the maximum divisor */ in clk_fd_test_approximation_max_denominator_zero_based()
107 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; in clk_fd_test_approximation_max_numerator_zero_based() local
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A Dclk-si5351.c276 rate /= 8; in si5351_clkin_recalc_rate()
279 rate /= 4; in si5351_clkin_recalc_rate()
282 rate /= 2; in si5351_clkin_recalc_rate()
293 return rate; in si5351_clkin_recalc_rate()
450 unsigned long rate = req->rate; in si5351_pll_determine_rate() local
500 req->rate = rate; in si5351_pll_determine_rate()
653 unsigned long rate = req->rate; in si5351_msynth_determine_rate() local
758 req->rate = rate; in si5351_msynth_determine_rate()
1048 unsigned long rate = req->rate; in si5351_clkout_determine_rate() local
1068 rate *= 2; in si5351_clkout_determine_rate()
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/drivers/staging/rtl8723bs/include/
A Dhal_com.h49 #define HDATA_RATE(rate)\ argument
50 (rate == DESC_RATE1M) ? "CCK_1M" : \
51 (rate == DESC_RATE2M) ? "CCK_2M" : \
62 (rate == DESC_RATEMCS0) ? "MCS0" : \
63 (rate == DESC_RATEMCS1) ? "MCS1" : \
64 (rate == DESC_RATEMCS2) ? "MCS2" : \
65 (rate == DESC_RATEMCS3) ? "MCS3" : \
66 (rate == DESC_RATEMCS4) ? "MCS4" : \
67 (rate == DESC_RATEMCS5) ? "MCS5" : \
112 u8 MRateToHwRate(u8 rate);
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/drivers/clk/sunxi-ng/
A Dccu_nm.c22 u64 rate = parent; in ccu_nm_calc_rate() local
24 rate *= n; in ccu_nm_calc_rate()
25 do_div(rate, m); in ccu_nm_calc_rate()
27 return rate; in ccu_nm_calc_rate()
81 unsigned long rate; in ccu_nm_recalc_rate() local
91 return rate; in ccu_nm_recalc_rate()
116 return rate; in ccu_nm_recalc_rate()
129 req->rate = nm->min_rate; in ccu_nm_determine_rate()
160 req->rate, &_nm); in ccu_nm_determine_rate()
178 rate = rate * nm->fixed_post_div; in ccu_nm_set_rate()
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A Dccu_mp.c36 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
87 return rate; in ccu_mp_find_best_with_parent_adj()
98 return rate; in ccu_mp_find_best_with_parent_adj()
130 rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, shift, in ccu_mp_round_rate()
133 rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, in ccu_mp_round_rate()
140 return rate; in ccu_mp_round_rate()
195 return rate; in ccu_mp_recalc_rate()
232 rate = rate * cmp->fixed_post_div; in ccu_mp_set_rate()
308 return rate; in ccu_mp_mmc_recalc_rate()
320 req->rate *= 2; in ccu_mp_mmc_determine_rate()
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/drivers/clk/imx/
A Dclk-pll14xx.c100 if (rate == rate_table[i].rate) in imx_get_pll_settings()
156 t->rate = tt->rate; in imx_pll14xx_calc_settings()
174 if (rate >= rate_min && rate <= rate_max) { in imx_pll14xx_calc_settings()
215 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv, in imx_pll14xx_calc_settings()
228 if (req->rate >= rate_table[i].rate) { in clk_pll1416x_determine_rate()
229 req->rate = rate_table[i].rate; in clk_pll1416x_determine_rate()
235 req->rate = rate_table[pll->rate_count - 1].rate; in clk_pll1416x_determine_rate()
248 req->rate = t.rate; in clk_pll1443x_determine_rate()
282 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; in clk_pll14xx_mp_change()
302 if (!rate) { in clk_pll1416x_set_rate()
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A Dclk-pllv3.c125 req->rate = (req->rate >= parent_rate * 22) ? parent_rate * 22 : parent_rate * 20; in clk_pllv3_determine_rate()
177 if (req->rate > max_rate) in clk_pllv3_sys_determine_rate()
178 req->rate = max_rate; in clk_pllv3_sys_determine_rate()
180 req->rate = min_rate; in clk_pllv3_sys_determine_rate()
196 if (rate < min_rate || rate > max_rate) in clk_pllv3_sys_set_rate()
243 if (req->rate > max_rate) in clk_pllv3_av_determine_rate()
244 req->rate = max_rate; in clk_pllv3_av_determine_rate()
246 req->rate = min_rate; in clk_pllv3_av_determine_rate()
277 if (rate < min_rate || rate > max_rate) in clk_pllv3_av_set_rate()
283 div = rate / parent_rate; in clk_pllv3_av_set_rate()
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/drivers/clk/samsung/
A Dclk-pll.c45 if (rate == rate_table[i].rate) in samsung_get_pll_settings()
246 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
258 if (!rate) { in samsung_pll35xx_set_rate()
371 if (!rate) { in samsung_pll36xx_set_rate()
486 if (!rate) { in samsung_pll0822x_set_rate()
575 if (!rate) { in samsung_pll0831x_set_rate()
672 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
685 if (!rate) { in samsung_pll45xx_set_rate()
809 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
822 if (!rate) { in samsung_pll46xx_set_rate()
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/drivers/net/wireless/realtek/rtw88/
A Dphy.c1540 u8 rate; in rtw_phy_store_tx_power_by_rate() local
2009 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) in rtw_phy_get_2g_tx_power_index()
2125 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M) in rtw_phy_rate_to_rate_section()
2127 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) in rtw_phy_rate_to_rate_section()
2129 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7) in rtw_phy_rate_to_rate_section()
2131 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) in rtw_phy_rate_to_rate_section()
2172 if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31) in rtw_phy_get_tx_power_limit()
2292 u8 rate; in rtw_phy_set_tx_power_index_by_rs() local
2352 u8 rate; in rtw_phy_tx_power_by_rate_config_by_path() local
2364 for (rate = 0; rate < size; rate++) { in rtw_phy_tx_power_by_rate_config_by_path()
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/drivers/clk/qcom/
A Dclk-rcg2.c185 rate = mult_frac(rate, 2, hid_div + 1); in calc_rate()
188 rate = mult_frac(rate, m, n); in calc_rate()
190 return rate; in calc_rate()
233 unsigned long clk_flags, rate = req->rate; in _freq_tbl_determine_rate() local
264 if (!rate) in _freq_tbl_determine_rate()
265 rate = req->rate; in _freq_tbl_determine_rate()
266 rate /= 2; in _freq_tbl_determine_rate()
346 unsigned long clk_flags, rate = req->rate; in _freq_tbl_fm_determine_rate() local
372 rate = req->rate; in _freq_tbl_fm_determine_rate()
1053 unsigned long rate = req->rate; in clk_byte2_determine_rate() local
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/drivers/clk/meson/
A Dclk-pll.c59 u64 rate = (u64)parent_rate * m; in __pll_params_to_rate() local
66 rate += DIV_ROUND_UP_ULL(frac_rate, frac_max); in __pll_params_to_rate()
69 return DIV_ROUND_UP_ULL(rate, n); in __pll_params_to_rate()
106 u64 val = (u64)rate * n; in __pll_params_with_frac()
109 if (rate < parent_rate * m / n) in __pll_params_with_frac()
129 if (abs(now - rate) < abs(best - rate)) in meson_clk_pll_is_better()
133 if (now <= rate && best < now) in meson_clk_pll_is_better()
159 u64 val = (u64)rate * n; in meson_clk_get_pll_range_m()
238 if (now == rate) in meson_clk_get_pll_settings()
263 req->rate = round; in meson_clk_pll_determine_rate()
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/drivers/net/wireless/intel/iwlwifi/fw/
A Drs.c99 u32 bw = (rate & RATE_MCS_CHAN_WIDTH_MSK) >> in rs_pretty_print_rate()
101 u32 format = rate & RATE_MCS_MOD_TYPE_MSK; in rs_pretty_print_rate()
110 index += rate & RATE_LEGACY_RATE_MSK; in rs_pretty_print_rate()
132 RATE_HT_MCS_INDEX(rate) : in rs_pretty_print_rate()
133 rate & RATE_MCS_CODE_MSK; in rs_pretty_print_rate()
134 nss = u32_get_bits(rate, RATE_MCS_NSS_MSK); in rs_pretty_print_rate()
136 iwl_he_is_sgi(rate) : in rs_pretty_print_rate()
137 rate & RATE_MCS_SGI_MSK; in rs_pretty_print_rate()
143 (rate & RATE_MCS_STBC_MSK) ? "STBC " : "", in rs_pretty_print_rate()
144 (rate & RATE_MCS_LDPC_MSK) ? "LDPC " : "", in rs_pretty_print_rate()
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/drivers/clk/at91/
A Dclk-audio-pll.c223 if (!rate) in clk_audio_pll_frac_compute_frac()
226 tmp = rate; in clk_audio_pll_frac_compute_frac()
253 req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX); in clk_audio_pll_frac_determine_rate()
286 rate, *parent_rate); in clk_audio_pll_pad_round_rate()
336 rate, *parent_rate); in clk_audio_pll_pmc_round_rate()
338 if (!rate) in clk_audio_pll_pmc_round_rate()
374 if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX) in clk_audio_pll_frac_set_rate()
394 rate, parent_rate); in clk_audio_pll_pad_set_rate()
396 if (!rate) in clk_audio_pll_pad_set_rate()
416 if (!rate) in clk_audio_pll_pmc_set_rate()
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/drivers/memory/tegra/
A Dtegra20-emc.c181 unsigned long rate; member
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
286 __func__, timing->rate, rate); in emc_prepare_timing_change()
359 u32 rate; in load_one_timing_from_dt() local
388 timing->rate = rate * 2 * 1000; in load_one_timing_from_dt()
401 if (a->rate < b->rate) in cmp_timings()
404 if (a->rate > b->rate) in cmp_timings()
687 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
820 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
994 rate = min_t(u64, rate, U32_MAX); in emc_icc_set()
[all …]
/drivers/clk/tegra/
A Dclk-tegra-super-cclk.c46 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
75 long rate = req->rate; in cclk_super_determine_rate() local
86 if (rate <= pllp_rate) { in cclk_super_determine_rate()
88 rate = pllp_rate; in cclk_super_determine_rate()
91 .rate = req->rate, in cclk_super_determine_rate()
99 rate = parent.rate; in cclk_super_determine_rate()
104 req->rate = rate; in cclk_super_determine_rate()
106 rate = clk_hw_round_rate(pllx_hw, rate); in cclk_super_determine_rate()
107 req->best_parent_rate = rate; in cclk_super_determine_rate()
109 req->rate = rate; in cclk_super_determine_rate()
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