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/drivers/gpu/drm/amd/display/dc/sspl/
A Ddc_spl.c462 spl_scratch->scl_data.ratios.horz_c = spl_scratch->scl_data.ratios.horz; in spl_calculate_scaling_ratios()
463 spl_scratch->scl_data.ratios.vert_c = spl_scratch->scl_data.ratios.vert; in spl_calculate_scaling_ratios()
484 spl_scratch->scl_data.ratios.horz); in spl_calculate_scaling_ratios()
676 spl_scratch->scl_data.ratios.horz, in spl_calculate_inits_and_viewports()
698 spl_scratch->scl_data.ratios.vert, in spl_calculate_inits_and_viewports()
764 if (data->ratios.horz.value == one in spl_get_dscl_mode()
765 && data->ratios.vert.value == one in spl_get_dscl_mode()
1182 dscl_prog_data->ratios.h_scale_ratio = spl_fixpt_u3d19(scl_data->ratios.horz) << 5; in spl_set_manual_ratio_init_data()
1183 dscl_prog_data->ratios.v_scale_ratio = spl_fixpt_u3d19(scl_data->ratios.vert) << 5; in spl_set_manual_ratio_init_data()
1184 dscl_prog_data->ratios.h_scale_ratio_c = spl_fixpt_u3d19(scl_data->ratios.horz_c) << 5; in spl_set_manual_ratio_init_data()
[all …]
A Ddc_spl_scl_easf_filters.c2361 data->taps.h_taps, data->ratios.horz); in spl_set_filters_data()
2364 data->taps.h_taps_c, data->ratios.horz_c); in spl_set_filters_data()
2374 data->taps.v_taps, data->ratios.vert); in spl_set_filters_data()
2377 data->taps.v_taps_c, data->ratios.vert_c); in spl_set_filters_data()
A Ddc_spl_types.h139 struct spl_ratios ratios; member
261 struct ratio ratios; member
/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.c208 if (scl_data->ratios.horz.value == (8ll << 32)) in dpp201_get_optimal_number_of_taps()
209 scl_data->ratios.horz.value--; in dpp201_get_optimal_number_of_taps()
211 scl_data->ratios.vert.value--; in dpp201_get_optimal_number_of_taps()
213 scl_data->ratios.horz_c.value--; in dpp201_get_optimal_number_of_taps()
215 scl_data->ratios.vert_c.value--; in dpp201_get_optimal_number_of_taps()
219 if (dc_fixpt_ceil(scl_data->ratios.horz) > 4) in dpp201_get_optimal_number_of_taps()
227 if (dc_fixpt_ceil(scl_data->ratios.vert) > 4) in dpp201_get_optimal_number_of_taps()
252 if (IDENTITY_RATIO(scl_data->ratios.horz)) in dpp201_get_optimal_number_of_taps()
254 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp201_get_optimal_number_of_taps()
256 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) in dpp201_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_dscl.c136 if (data->ratios.horz.value == one in dpp1_dscl_get_dscl_mode()
137 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
138 && data->ratios.horz_c.value == one in dpp1_dscl_get_dscl_mode()
139 && data->ratios.vert_c.value == one in dpp1_dscl_get_dscl_mode()
149 if (data->ratios.horz.value == one && data->ratios.vert.value == one) in dpp1_dscl_get_dscl_mode()
151 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) in dpp1_dscl_get_dscl_mode()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
319 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
326 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); in dpp1_dscl_set_scl_filter()
328 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); in dpp1_dscl_set_scl_filter()
[all …]
A Ddcn10_dpp.c144 if (scl_data->ratios.horz.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
145 scl_data->ratios.horz.value--; in dpp1_get_optimal_number_of_taps()
146 if (scl_data->ratios.vert.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
147 scl_data->ratios.vert.value--; in dpp1_get_optimal_number_of_taps()
148 if (scl_data->ratios.horz_c.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
149 scl_data->ratios.horz_c.value--; in dpp1_get_optimal_number_of_taps()
151 scl_data->ratios.vert_c.value--; in dpp1_get_optimal_number_of_taps()
175 if (IDENTITY_RATIO(scl_data->ratios.horz)) in dpp1_get_optimal_number_of_taps()
177 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp1_get_optimal_number_of_taps()
179 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) in dpp1_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c138 if (data->ratios.horz.value == one in dpp401_dscl_get_dscl_mode()
139 && data->ratios.vert.value == one in dpp401_dscl_get_dscl_mode()
140 && data->ratios.horz_c.value == one in dpp401_dscl_get_dscl_mode()
141 && data->ratios.vert_c.value == one in dpp401_dscl_get_dscl_mode()
151 if (data->ratios.horz.value == one && data->ratios.vert.value == one) in dpp401_dscl_get_dscl_mode()
153 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) in dpp401_dscl_get_dscl_mode()
307 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp401_dscl_set_scl_filter()
309 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp401_dscl_set_scl_filter()
312 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); in dpp401_dscl_set_scl_filter()
314 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); in dpp401_dscl_set_scl_filter()
[all …]
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c50 static void populate_ratios_from_splratios(struct scaling_ratios *ratios, in populate_ratios_from_splratios() argument
53 ratios->horz = dc_fixpt_from_ux_dy(spl_ratios->h_scale_ratio >> 5, 3, 19); in populate_ratios_from_splratios()
54 ratios->vert = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio >> 5, 3, 19); in populate_ratios_from_splratios()
55 ratios->horz_c = dc_fixpt_from_ux_dy(spl_ratios->h_scale_ratio_c >> 5, 3, 19); in populate_ratios_from_splratios()
56 ratios->vert_c = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio_c >> 5, 3, 19); in populate_ratios_from_splratios()
220 …late_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios); in translate_SPL_out_params_to_pipe_ctx()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c286 dc_fixpt_u2d19(data->ratios.horz) << 5; in calculate_inits()
288 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
293 data->ratios.horz, in calculate_inits()
302 data->ratios.vert, in calculate_inits()
318 dc_fixpt_u2d19(data->ratios.horz) << 5; in dce60_calculate_inits()
320 dc_fixpt_u2d19(data->ratios.vert) << 5; in dce60_calculate_inits()
331 data->ratios.vert, in dce60_calculate_inits()
439 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
440 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
1199 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { in dce_transform_get_optimal_number_of_taps()
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/drivers/clk/mvebu/
A Dorion.c80 .ratios = orion_coreclk_ratios,
148 .ratios = orion_coreclk_ratios,
205 .ratios = orion_coreclk_ratios,
268 .ratios = orion_coreclk_ratios,
A Dkirkwood.c197 .ratios = kirkwood_coreclk_ratios,
205 .ratios = kirkwood_coreclk_ratios,
213 .ratios = kirkwood_coreclk_ratios,
A Dcommon.c157 const char *rclk_name = desc->ratios[n].name; in mvebu_coreclk_setup()
162 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); in mvebu_coreclk_setup()
A Dcommon.h34 const struct coreclk_ratio *ratios; member
A Darmada-375.c136 .ratios = armada_375_coreclk_ratios,
A Darmada-39x.c123 .ratios = armada_39x_coreclk_ratios,
A Darmada-38x.c120 .ratios = armada_38x_coreclk_ratios,
A Dmv98dx3236.c149 .ratios = mv98dx3236_core_ratios,
A Ddove.c152 .ratios = dove_coreclk_ratios,
A Darmada-370.c146 .ratios = a370_coreclk_ratios,
A Darmada-xp.c154 .ratios = axp_coreclk_ratios,
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.c434 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) in dpp3_get_optimal_number_of_taps()
441 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) in dpp3_get_optimal_number_of_taps()
448 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) in dpp3_get_optimal_number_of_taps()
455 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1) in dpp3_get_optimal_number_of_taps()
472 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); in dpp3_get_optimal_number_of_taps()
485 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) in dpp3_get_optimal_number_of_taps()
490 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2) in dpp3_get_optimal_number_of_taps()
507 if (IDENTITY_RATIO(scl_data->ratios.horz)) in dpp3_get_optimal_number_of_taps()
509 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp3_get_optimal_number_of_taps()
511 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) in dpp3_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_transform_v.c375 dc_fixpt_u2d19(data->ratios.horz) << 5; in calculate_inits()
377 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
379 dc_fixpt_u2d19(data->ratios.horz_c) << 5; in calculate_inits()
381 dc_fixpt_u2d19(data->ratios.vert_c) << 5; in calculate_inits()
559 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
560 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
561 coeffs_v_c = get_filter_coeffs_64p(data->taps.v_taps_c, data->ratios.vert_c); in dce110_xfmv_set_scaler()
562 coeffs_h_c = get_filter_coeffs_64p(data->taps.h_taps_c, data->ratios.horz_c); in dce110_xfmv_set_scaler()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c1156 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1165 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios()
1166 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
1174 pipe_ctx->plane_res.scl_data.ratios.horz, 19); in calculate_scaling_ratios()
1176 pipe_ctx->plane_res.scl_data.ratios.vert, 19); in calculate_scaling_ratios()
1178 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); in calculate_scaling_ratios()
1180 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); in calculate_scaling_ratios()
1298 data->ratios.horz, in calculate_inits_and_viewports()
1308 data->ratios.horz_c, in calculate_inits_and_viewports()
1318 data->ratios.vert, in calculate_inits_and_viewports()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c892 plane->composition.scaler_info.enabled = scaler_data->ratios.horz.value != dc_fixpt_one.value || in populate_dml21_plane_config_from_plane_state()
893 scaler_data->ratios.horz_c.value != dc_fixpt_one.value || in populate_dml21_plane_config_from_plane_state()
894 scaler_data->ratios.vert.value != dc_fixpt_one.value || in populate_dml21_plane_config_from_plane_state()
895 scaler_data->ratios.vert_c.value != dc_fixpt_one.value; in populate_dml21_plane_config_from_plane_state()
924 …plane->composition.scaler_info.plane0.h_ratio = (double)scaler_data->ratios.horz.value / (1ULL << … in populate_dml21_plane_config_from_plane_state()
925 …plane->composition.scaler_info.plane0.v_ratio = (double)scaler_data->ratios.vert.value / (1ULL << … in populate_dml21_plane_config_from_plane_state()
926 …plane->composition.scaler_info.plane1.h_ratio = (double)scaler_data->ratios.horz_c.value / (1ULL <… in populate_dml21_plane_config_from_plane_state()
927 …plane->composition.scaler_info.plane1.v_ratio = (double)scaler_data->ratios.vert_c.value / (1ULL <… in populate_dml21_plane_config_from_plane_state()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
407 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
408 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
977 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value in dcn_validate_bandwidth()
979 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
982 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value in dcn_validate_bandwidth()
984 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()

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