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Searched refs:rc_quant_incr_limit0 (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c46 to->rc_quant_incr_limit0 = from->rc_quant_incr_limit0; in copy_pps_fields()
75 dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; in copy_rc_to_cfg()
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c225 pps_payload->rc_quant_incr_limit0 = in drm_dsc_pps_payload_pack()
226 dsc_cfg->rc_quant_incr_limit0; in drm_dsc_pps_payload_pack()
338 u8 rc_quant_incr_limit0; member
1282 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; in drm_dsc_setup_rc_params()
1508 cfg->rc_edge_factor, cfg->rc_quant_incr_limit0, cfg->rc_quant_incr_limit1); in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/amd/display/dc/dml/dsc/
A Drc_calc_fpu.h37 int rc_quant_incr_limit0; member
A Drc_calc_fpu.c189 …rc->rc_quant_incr_limit0 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == … in _do_calc_rc_params()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c320 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); in dsc_log_pps()
351 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0; in dsc_override_rc_params()
554 reg_vals->pps.rc_quant_incr_limit0 = 11; in dsc_init_reg_values()
681 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, in dsc_write_to_registers()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c123 data |= dsc->rc_quant_incr_limit0 << 4; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c214 data |= (dsc->rc_quant_incr_limit0 & 0x1f) << 8; in dpu_hw_dsc_config_1_2()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c142 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; in calculate_rc_params()
537 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | in intel_dsc_pps_configure()
958 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dintel_display.c5409 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0); in intel_pipe_config_compare()
/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h849 int32_t rc_quant_incr_limit0; member
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c303 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, in dsc_write_to_registers()

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