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Searched refs:rc_quant_incr_limit1 (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c45 to->rc_quant_incr_limit1 = from->rc_quant_incr_limit1; in copy_pps_fields()
76 dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; in copy_rc_to_cfg()
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c229 pps_payload->rc_quant_incr_limit1 = in drm_dsc_pps_payload_pack()
230 dsc_cfg->rc_quant_incr_limit1; in drm_dsc_pps_payload_pack()
339 u8 rc_quant_incr_limit1; member
1283 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; in drm_dsc_setup_rc_params()
1508 cfg->rc_edge_factor, cfg->rc_quant_incr_limit0, cfg->rc_quant_incr_limit1); in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/amd/display/dc/dml/dsc/
A Drc_calc_fpu.h38 int rc_quant_incr_limit1; member
A Drc_calc_fpu.c190 …rc->rc_quant_incr_limit1 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == … in _do_calc_rc_params()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c321 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); in dsc_log_pps()
352 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1; in dsc_override_rc_params()
555 reg_vals->pps.rc_quant_incr_limit1 = 11; in dsc_init_reg_values()
682 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, in dsc_write_to_registers()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c122 data |= dsc->rc_quant_incr_limit1 << 9; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c215 data |= (dsc->rc_quant_incr_limit1 & 0x1f) << 13; in dpu_hw_dsc_config_1_2()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c143 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; in calculate_rc_params()
538 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | in intel_dsc_pps_configure()
959 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dintel_display.c5410 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1); in intel_pipe_config_compare()
/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h850 int32_t rc_quant_incr_limit1; member
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c304 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, in dsc_write_to_registers()

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