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Searched refs:reader_wm_sets (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
468 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges()
469 …ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MA… in build_watermark_ranges()
472 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { in build_watermark_ranges()
474 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; in build_watermark_ranges()
479 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
483 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges()
484 …ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MA… in build_watermark_ranges()
497 ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()
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/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c478 if (ranges->reader_wm_sets[i].wm_inst > 3) in pp_rv_set_wm_ranges()
482 ranges->reader_wm_sets[i].wm_inst; in pp_rv_set_wm_ranges()
484 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
486 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
488 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
490 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c1392 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1404 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1405 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300; in dcn_bw_notify_pplib_of_wm_ranges()
1406 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()
1407 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800; in dcn_bw_notify_pplib_of_wm_ranges()
1408 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()
1416 ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0]; in dcn_bw_notify_pplib_of_wm_ranges()
1417 ranges.reader_wm_sets[1].wm_inst = WM_B; in dcn_bw_notify_pplib_of_wm_ranges()
1419 ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0]; in dcn_bw_notify_pplib_of_wm_ranges()
1420 ranges.reader_wm_sets[2].wm_inst = WM_C; in dcn_bw_notify_pplib_of_wm_ranges()
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/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c1332 ranges.reader_wm_sets[0].wm_inst = 0; in set_wm_ranges()
1333 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1334 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1335 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1336 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1341 ranges.reader_wm_sets[i].wm_inst = i; in set_wm_ranges()
1342 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1343 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1350 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1351 …ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UN… in set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_5_ppt.c425 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v13_0_5_set_watermarks_table()
427 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v13_0_5_set_watermarks_table()
429 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
431 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
434 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v13_0_5_set_watermarks_table()
A Dsmu_v13_0_4_ppt.c679 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v13_0_4_set_watermarks_table()
681 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v13_0_4_set_watermarks_table()
683 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
685 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
688 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v13_0_4_set_watermarks_table()
A Dyellow_carp_ppt.c516 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in yellow_carp_set_watermarks_table()
518 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in yellow_carp_set_watermarks_table()
520 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()
522 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in yellow_carp_set_watermarks_table()
525 clock_ranges->reader_wm_sets[i].wm_inst; in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c1075 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in renoir_set_watermarks_table()
1077 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in renoir_set_watermarks_table()
1079 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()
1081 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in renoir_set_watermarks_table()
1084 clock_ranges->reader_wm_sets[i].wm_inst; in renoir_set_watermarks_table()
1086 clock_ranges->reader_wm_sets[i].wm_type; in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c2574 ranges.reader_wm_sets[0].wm_inst = i; in dcn20_resource_construct()
2575 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2576 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2577 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2578 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2583 ranges.reader_wm_sets[i].wm_inst = i; in dcn20_resource_construct()
2584 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2585 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2593 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2594 …ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UN… in dcn20_resource_construct()
/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h91 struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS]; member
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c394 …ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_… in dcn301_fpu_set_wm_ranges()
395 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in dcn301_fpu_set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c498 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
500 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
502 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
504 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
507 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v14_0_0_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c1607 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in vangogh_set_watermarks_table()
1609 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in vangogh_set_watermarks_table()
1611 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()
1613 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in vangogh_set_watermarks_table()
1616 clock_ranges->reader_wm_sets[i].wm_inst; in vangogh_set_watermarks_table()
A Dsienna_cichlid_ppt.c1887 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1889 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1891 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1893 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1896 clock_ranges->reader_wm_sets[i].wm_inst; in sienna_cichlid_set_watermarks_table()
A Dnavi10_ppt.c2185 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in navi10_set_watermarks_table()
2187 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in navi10_set_watermarks_table()
2189 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()
2191 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in navi10_set_watermarks_table()
2194 clock_ranges->reader_wm_sets[i].wm_inst; in navi10_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c2137 …ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_… in dcn20_fpu_set_wm_ranges()
2138 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in dcn20_fpu_set_wm_ranges()

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